FPGAs Cross Scale Threshold to Enable True FPGA-based Verification

See full version of this article on EETimes.

The news is out! Aldec is adopting Xilinx® Virtex® UltraScale™ devices in its seventh generation Hardware Emulation Solution, HES-7™, heralding a great leap in the capability of FPGA-based verification.

FPGA-based Verification is here

This article announces that the scale of the latest FPGA technology is paving the way towards true FPGA-based Verification, as a serious alternative to big-box emulation.

Historically, some verification teams have tried to compensate for lack of emulation by using their FPGA-based prototypes as a substitute. FPGA-based prototypes are excellent not only for system validation, but also as platforms for early software development and in-field trials but, what else is needed to turn them into an FPGA-based verification platform?

Are Dual-Purpose FPGA Platforms a realistic expectation?

There are significant technical differences between using FPGAs for prototyping and using them for emulation, and dual-purpose FPGA systems that are good for both tasks have been rare indeed. Dual-use FPGA hardware requires considerable design effort and planning, but the reward is a platform that can take its place at the heart of a prototype or a verification environment equally well.

Considering the extra expertise and infrastructure needed for interfacing with simulators, the latter task is the more complex, and we should probably expect most progress on dual-use to be made from those coming from the verification camp, rather than those specializing only in the FPGA hardware.

Aldec has been successfully doing exactly that for over a decade, using FPGAs in multiple generations of their Hardware Emulation Solution platforms (that’s where the HES name comes from).

Introducing HES-7, employing Xilinx® Virtex® UltraScale™ Devices.

In the HES7XV12000 board, Aldec already has the largest capacity single FPGA boards commercially available and in use today. The HES7XV12000 platform gives Aldec’s Hardware development team a great starting point for taking FPGA systems to a whole new scale. Replacing the six XC7V2000T FPGAs one-for-one with Xilinx’s latest Virtex® UltraScale™-440 devices (VU440, for short), the resultant boards are quite simply the largest and most capable FPGA platforms ever made available. The development of a new FPGA platform isn’t really quite that simple, but you get the picture.

Each VU440 device is published as containing resources for implementing 50M ASIC gates, and whereas this may be demonstrably correct for certain designs, Aldec follows the common-sense guideline of staying well within the upper limit of resource usage, in order to maximize ease-of-use. As such, Aldec users should safely expect each HES-7 with Xilinx UltraScale Devices to implement 160M ASIC gates of SoC design, which breaks Aldec’s own industry record. Many designs may exceed this ease-of-use guideline, and Aldec engineers can tell you how, but 160M for FPGA-based Verification is a good expectation.

Harnessing FPGA capability using HES-DVM

All that vast FPGA resource is harnessed into an SoC verification environment via Aldec’s HES Design Verification Manager suite of tools, or HES-DVM™. HES-DVM provides all the IP libraries, SCE-MI transactors, compilers, and mappers required in order to automatically integrate HES-7 FPGA platforms with the proven Aldec verification environment. This allows properly designed FPGA hardware to be employed with a wide range of simulators, debuggers, and testbenches, from simple RTL directed tests, right up to and including advanced UVM test rigs.

Aldec’s HES-7 and HES-DVM are the best way to reduce risk and shorten bring-up time, and make budget-saving dual-use of that FPGA platform.

Why are big FPGAs big news?

In general, emulators only use a fraction of their hardware resources, and this is also true for FPGA-based verification. There are good reasons this, but it means that emulator capacity needs to be as large as possible to handle today’s complex designs, and also to allow for design growth. However, we won’t need all that resource for early block level tests, or also use in FPGA-based prototype mode, which is mapped more efficiently. This difference in required capacity for different stages of the project is best accommodated by adopting a scalable methodology.

Scalability is achieved by a modular approach with smaller platforms in use in early stages of the project, being assembled into larger systems as more of the SoC design is simulated, and later emulated. If project schedules and resources allow, then these same FPGA platforms might be re-used as distributed stand-alone FPGA-based prototype, as illustrated in the diagram, in which we see the project maturing in time across the horizontal, from left to right; hardware at the bottom, software on the top.

The secret sauce of this whole approach is scale and scalability.

Read more about “Scale and Scalability” on EETimes.

As we have seen, FPGAs are an extremely flexible platform for the verification of SoC designs, at all levels of the design, and at all staged of the project. You can read more about it on an extended version of this article by Doug Amos, @dougfpga, author of the FPGA-based Prototyping Methodology Manual, published by EETimes.

More to come . . .

We will explore some of the concepts introduced in this short overview in more detail in further articles to follow.

For datasheets and more information you can also visit www.aldec.com/products/hes-dvm or contact Aldec Sales at +1-702-990-4400 or sales@aldec.com.