Event Details View All Recorded Events Date Event Type Location Action Aug 20, 2026 Practical Co-Simulation Techniques with OSVVM Part 1: Getting Started with OSVVM Co-Simulation (EU) Time: 4:00 PM - 5:00 PM (CEST) Webinar Overview OSVVM is a powerful open-source VHDL verification methodology and library, widely adopted for FPGA and SoC verification. It provides a comprehensive set of capabilities including transaction-based verification, constrained randomization, functional coverage, scoreboards, memory models, reusable testbench architectures, and advanced scripting support across leading simulators such as Aldec’s Active-HDL and Riviera-PRO. With the introduction of co-simulation support in OSVVM 2023.01, verification engineers can now integrate native C and C++ applications directly into VHDL simulation environments, enabling faster development and more advanced verification workflows. In this, the first webinar in a three-part series, we introduce the fundamentals of OSVVM co-simulation and demonstrate how software-driven verification can be integrated into existing OSVVM testbenches. Attendees will learn how co-simulation fits into the OSVVM framework, how to build and connect co-simulation applications, and how to compile and execute mixed-language verification environments using Riviera-PRO. Attendees will also see a live demonstration of running a JPEG image processing co-simulation test running in Riviera-PRO, highlighting practical workflows and real-world verification techniques. Agenda: Introduction to OSVVM Co-Simulation Why Co-Simulation Matters in Modern Verification Review of Traditional OSVVM MIT/VC Testbenches VHDL Co-Simulation Interfaces and Procedures C/C++ Co-Simulation APIs Building a Co-Simulation Application Compiling and Running Mixed-Language Testbenches Demonstration: Running a JPEG image processing co-simulation test using the gtk graphics toolkit external library Best Practices and Debug Techniques Q&A Webinar Duration: 45 min presentation/live demo 15 min Q&A Presenter BIO Simon Southwell, Freelance Logic and Software Consultant, specializing in co-simulation, HPC and wireless solutionsSimon Southwell, Freelance Logic and Software Consultant, specializing in co-simulation, HPC, and wireless solutions. Engineer with 35 years in Research and Development, with experience in ASIC design, FPGA, and embedded software development. Now spending time contributing IP to the open-source community, and sharing experience and knowledge through writing articles and mentoring undergraduates and junior engineers. Also, currently a collaborator on the OSVVM project, a verification methodology and VHDL library, adding and supporting its co-simulation capabilities. Particular areas of interest include processor systems and sub-systems, system modelling in software, the software/hardware interface, and co-simulation of logic and software. Amongst the many areas of experiences are original logic IP design targeting both ASIC and FPGA, logic verification, HPC (supercomputers), processor systems, networking (802.3 and proprietary), embedded software, co-simulation technology, software modelling of SoC systems, data compression logic, PCIe endpoint design, cellular (3G and 4G), wireless (802.11 and 802.15.4), and more. Joint or sole author on several logic IP-related patents. Webinar Online Register
