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100% Signal Visibility during Emulation Dynamic Debug with HVD Technology   
Abstract: When it comes to debugging during emulation, engineers are forced to use multiple applications to ensure proper hardware signal data extraction and visualization. Learn from this webinar a leading edge technology that intelligently extracts data from the FPGA emulator to provide 100% signal visibility during emulation. This approach delivers up to 70% bandwidth savings in the critical emulator communication channel. Both dynamic and static probes from emulation can also be visualized in the Riviera-PRO waveform viewer preserving the original signal names and hierarchy paths and providing complete traceability to the design’s RTL source code. Play webinar   
HES-DVM Recorded Webinars
Accelerate DSP Design Development: Tailored Flows   
Learn how to achieve better Digital Signal Processing (DSP) design productivity using Aldec’s integrated design flows, enabled by a number of unique technologies, features, and industry partnerships available within Aldec Riviera-PRO™ design and verification platform. You will learn about the essential and innovative features in the RTL simulation environment that are important to signal processing: Model-based design flow integration, Floating-point aware RTL debugging tools, Dedicated protocol analysis tools, Full support for FPGA silicon vendors. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Accelerate SoC Simulation Time of Newer Generation FPGAs   
Functional verification of a design at the three design stages (RTL, Gate-Level and Post-Route) are essential steps to ensure correct behavior of a design according to requirements, however they are limited by HDL simulator speed. While HDL simulators offer advanced debugging capabilities and provide robust design coverage information, their speed is the primary bottleneck of the design cycle when it comes to verification. This webinar will discuss a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. Play webinar   
HES-DVM, HES-7 Recorded Webinars
Accelerating Large Image and Signal Processing FPGA Design Developments with TySOM-3A-ZU19EG and PYNQ   
Developing for larger Heterogeneous SoC like the Xilinx MPSoC UltraScale+ EG19 device present the developer with several challenges, from timing closure to developing the software and demonstrating increasing technology readiness level (TRL) as the product develops. One of the largest challenges if the integration of the programmable logic algorithm with the application software, this needs to not only correctly be able to configure and access design elements implemented in the programmable logic but also implement the higher-level algorithms and application. TySOM embedded development board enables the developer to hit the ground running and start developing the application for both the programmable logic and software solution from day one. By leveraging the PYNQ framework the developers can accelerate the development of algorithms and verification of programmable logic design. PYNQ provides the developer with the ability to control AXI peripherals within the programmable logic using Python and Jupyter notebooks, opening the wider python ecosystem for development and verification of the algorithms. This is especially beneficial for image and signal processing applications. This session will demonstrate how developers can use the TySOM-3A-ZU19EG embedded development board and the PYNQ framework can be combined to accelerate your developments for image and signal processing applications. Play webinar   
TySOM Boards Recorded Webinars
Accelerating The Verification Of Hardware Dependent Software   
Software costs now dominate in SoC design. It is therefore imperative that the dependencies the hardware places on the software are captured and managed as early as possible. To ignore these is to risk project and budget overrun. In this webinar, we will illustrate why FPGAs are chosen as the verification platform for software integration. We will discuss the challenges of using FPGAs for verification and introduce the use of hybrid virtual prototypes. A comparison will be made between traditional FPGA ASIC prototypes and an FPGA-based emulation system. Play webinar   
HES-DVM, HES-7 Recorded Webinars
Accelerating Verification Component development with OSVVM Model Independent Transactions   
Verification components have become an essential part of a structured VHDL environment. In OSVVM we implement verification components as an entity and architecture. This provides RTL engineers with a familiar environment to create model behavior.    The objective of any verification framework is to make the Device Under Test (DUT) "feel like" it has been plugged into the board. Hence, the framework must be able to produce the same waveforms and sequences of waveforms that the DUT will see on the board. The OSVVM testbench framework looks identical to other frameworks, including SystemVerilog. It includes verification components (AxiStreamTransmitter and AxiStreamReceiver) and TestCtrl (the test sequencer) as shown in Figure 1. The top level of the testbench connects the components together (using the same methods as in RTL design) and is often called a test harness. Connections between the verification components and TestCtrl use VHDL records (which we call the transaction interface).   Connections between the verification components and the DUT are the DUT interfaces (such as AxiStream, UART, AXI4, SPI, and I2C).   There are three steps required to create an OSVVM verification component: Define the transaction interface (in OSVVM it is a record) Define the transaction procedures (the call API for the test sequencer) Define the internals of the verification component itself.   OSVVM model independent transactions are one of our latest innovations – added to OSVVM in 2020.07. For a class of interfaces, the model independent transactions define the transaction interface and transaction procedures. OSVVM has defined these for address bus interfaces (such as AXI, Avalon, X86, …) and streaming type interfaces (such as UART, AXI Stream, …).    For a testbench/verification component developer, using the model independent transactions allows a developer to focus on just the internals of the verification component. Directive transactions can be copied from models of a similar class. This helps save time in testbench development. For the test case developer, model independent transactions provide address bus interfaces and streaming interfaces with a common set of transactions (API). This makes writing test cases easier since the transaction interface (API) is already familiar.  This also facilitates either re-use of test sequences between different verification components or porting tests from one interface to another.    This webinar provides a guided walk-through of the OSVVM model independent transactions. Benefits of OSVVM OSVVM is a competitive solution with SystemVerilog + UVM for FPGA Verification.   World-wide, 18% of the FPGA market uses OSVVM [1] – or alternately 36% of the VHDL FPGA market uses OSVVM. In Europe, in the FPGA market, OSVVM (with 36%) leads SystemVerilog+UVM (with 26%).     OSVVM is an innovator and leader in the development of VHDL Verification Methodology. Our approach has been evolving in SynthWorks classes since 1997 and started being released as open source in 2011. So how does it compare to SystemVerilog? Constrained Random – Supported via RandomPkg and coding styles – an OSVVM innovation Functional Coverage – Supported via CoveragePkg – an OSVVM innovation Scoreboards – Supported via ScoreboardGenericPkg – an OSVVM innovation Error reporting and Messaging – supported via AlertLogPkg – concepts borrowed from numerous sources Transaction based testbenches and verification components – in our classes since 1997 Memory Modeling – data structure for efficient creation of memories through sparse allocation. Process Synchronization – barrier synchronization (an OSVVM innovation) as well as other methods. Is OSVVM supported by my simulator? Currently OSVVM is supported by simulators from Mentor, Aldec, Cadence, Synopsys, and GHDL. This is great support and our goal is to keep it this way. When we upgrade existing features in the library, we test to make sure we do not break support within our community. OTOH, when we introduce new capability (generally in separate packages) and there is a significant advantage to using advanced VHDL constructs – such as it simplifies how the item is used, then it is likely we will use it – as a result, some of OSVVM's Verification IP uses records with unconstrained arrays.  We also strictly avoid using deprecated language features - such as shared variables that have an ordinary type. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Achieve DO-254 Compliance with the Industry’s Most Comprehensive HDL Coding Guidelines   
The ALINT-PRO Static Design Verification solution includes DO-254 HDL Ruleset targeted for safety critical designs that require DO-254 compliance. Recently, this DO-254 Ruleset was enhanced with more than 80 new rules, adding a significant amount of code checks for Verilog and VHDL-based designs relevant to coding practices, clock domain crossings, safe synthesis, and code reviews. This webinar will provide an overview of the newly added DO-254 rules, from their specification to implementation and code examples. We will also discuss the available tool qualification data package for ALINT-PRO.  Play webinar   
ALINT-PRO Recorded Webinars
Addressing the Challenges of SoC Verification in practice using Co-Simulation   
Heterogeneous System on Chip (SoC) devices like the Xilinx Zynq 7000 and Zynq UltraScale+ MPSoC combine a high-performance processing systems (PS) with state of the art programmable logic (PL). This combination allows system to be architected to provide an optimal solution. Verifying this interaction between the PS and PL presents a challenge to the design team. While each can be verified in isolation using QEMU for the PS and Riviera-PRO for the PL. The integration between the PS and PL all too often takes place late in the design cycle when the impact of addressing issues raised is larger in both time and cost. There is however, another way which is Co-Simulation, which can be performed early in the development cycle. This webinar will explore the challenges which are faced by SoC users, introduce the concept of Co-Simulation and its constituent parts along with demonstrating advanced debugging techniques. We will examine the required environment and pre-requisites needed to perform Co-Simulation. Detailed examples will then be presented to demonstrate basic and advanced debugging concepts. Based upon a Zynq implementing a Pulse Width Modulation IP core operating under SW control. We will look at examples which introduce basic Co-Simulation flow like waveform inspection along with advanced debugging aspects such as software and Hardware breakpoints and single stepping. These techniques will enable us to identify and debug issues which reside in both the software and hardware design. Co-Simulation enables you to develop your application faster and reduce the bring up time once the application hardware arrives for integration. This webinar will demonstrate these benefits and more which are gained when Co-Simulation is used, while demonstrating the ease with which the environment can be established and simulation performed. Play webinar   
Riviera-PRO, TySOM™ EDK Recorded Webinars
Advanced RTL Debugging for Zynq SoC Designs   
Presenter: Radek Nawrot, Aldec Software Product Manager

Abstract: Designers of complex embedded applications based on Xilinx® Zynq™ device require a high-performance RTL simulation and debugging platform. In this webinar, you will learn several advanced RTL debugging methodologies and techniques that you can employ for your block-level and system level simulation. You will learn how to use Dataflow, Code Coverage, Xtrace and Waveform Contributors for analyzing the errors in your AXI-based Zynq designs.

We welcome you to refer to the following Application Notes prior to the webinar:
Xilinx AXI-Based IP Overview
Simulating AXI BFM Examples Available in Xilinx CORE Generator
Simulating AXI-based Designs in Riviera-PRO
Performing Functional Simulation of Xilinx Zynq BFM in Riviera-PRO

Agenda
  • Embedded development flow between Xilinx Vivado™, SDK™, Riviera-PRO™ and TySOM™
  • Quick introduction to AXI
  • Running Riviera-PRO from Vivado
  • Code Coverage in simulation process
  • Advance dataflow- design overview
  • Bug injection – Xtrace in action
  • Waveform with Contributors – seek bug in code
 Play webinar   
Riviera-PRO, TySOM™ EDK Recorded Webinars
Aiding ASIC Design Partitioning for multi-FPGA Prototyping   
Whether it is an ASIC, ASSP or large FPGA design, emulation and prototyping are indispensable verification and validation activities. Often FPGA based platforms are chosen due to their scalability and versatility and more importantly, because of their runtime speed potential. What drives many away from this platform are the challenges of the multi-FPGA design setup that requires complex partitioning, arranging interconnections and managing multiple clock domains across multiple devices. Automation in this field is highly desirable to avoid time consuming and error prone hand-crafting and design hacks that would enable FPGA prototyping. Aldec HES™ Prototyping Platform and related solutions are here to mitigate these risks and facilitate rapid implementation of reliable FPGA prototypes. Design setup for a large multi-FPGA platform is facilitated with the HES-DVM tool that provides new partitioning utilities and can convert ASIC clocks to FPGA-proof structures. Awareness of clock domains and prototyping board connectivity resources facilitates in making wise decisions and allows achieving high clock ratios of FPGA prototypes. In this webinar, we will demonstrate the new HES-DVM prototyping flow that will increase your productivity in physical prototyping by shortening the setup time and increasing runtime speed of your design in FPGA.  Play webinar   
HES-DVM Recorded Webinars
Aldec and SynthWorks: OS-VVM: Open Source - VHDL Verification Methodology   
Open Source - VHDL Verification Methodology (OS-VVM™) provides advanced verification capabilities to VHDL teams. Attendees will learn how to add functional coverage, constrained random test, and coverage driven random test to their current testbenches. OS-VVM has a straight-forward usage model that allows the addition of functional coverage, constrained random, and coverage driven random features to a testbench in part or in whole. This webinar demonstrates how the addition of Functional Coverage to testbenches is necessary - even with directed tests. Constrained Random or Coverage Driven randomization can be added when and where needed, and there is even the ability to mix directed, algorithmic, file-based, constrained random, and coverage driven random methods. OS-VVM is open source package based. It compiles under VHDL-2008 or VHDL-2002 (with minor adaptations, and has been produced as a joint effort between Aldec and SynthWorks, both companies committed to provide continued support to VHDL design community. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
ARM Cortex SoC Prototyping Platform for Industrial Applications   
Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms allow designers to implement and verify functionality of industrial systems at-speed prior to silicon tape-out, saving money from costly re-spins. In this webinar, we demonstrate how to tackle industrial design applications with Aldec’s HES-7™, which supports ARM® Cortex™-A9 based designs by leveraging Xilinx® Zynq® All Programmable SoC. Play webinar   
HES-7 Recorded Webinars
ASIC/SoC Prototyping with Aldec’s new HES-7 Board   
Aldec's newly released FPGA-based prototyping platform, HES-7™, leverages Xilinx® Virtex®-7 FPGA. Xilinx has introduced a new Stacked Silicon Interconnect technology (SSI), enabling a single Virtex-7 to have 2M logic cells, making it the industry’s largest capacity FPGA. This webinar will provide an overview of modifications to previous Xilinx architecture and the structuring of SSI technology. The webinar will also present how the Virtex-7 benefits FPGA-based prototyping platforms, and will also provide an overview of HES-7 key features. Play webinar   
HES-7 Recorded Webinars
Assertions - A Practical Introduction for HDL Designers   
The majority of FPGA designers who are proficient in traditional HDLs might have heard about assertions, but haven’t had time to try them out. Designers should be aware that assertions are quickly becoming standard part of both design and verification process, so learning how to use them is a future necessity. This webinar provides quick and easy introduction to the basic ideas and applications of assertions: sequences, properties, assert and cover commands, etc. Practical examples are used both during presentation and live demonstration in the simulator. Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Best Design Practices for High-Capacity FPGA Devices   
With the latest FPGA technology advancements and release of high capacity devices such as Xilinx® Virtex®-7 and Altera® Stratix®-V, design teams face more challenges producing safe and clean HDL (RTL, FPGA) code. In this presentation, we will focus on the design techniques that will result in the code running most optimally on the large FPGA designs, and be free of timing and synchronization issues. Play webinar   
ALINT Recorded Webinars
Best Practices for DO-254 Requirements Traceability   
DO-254 enforces a strict requirements-driven process for the development of commercial airborne electronic hardware. For DO-254, requirements must drive the design and verification activities, and requirements traceability helps to ensure this. Learn in this webinar traceability best-practices for design assurance level (DAL) A FPGAs. We will provide insights to questions such as: What is the recommended approach when tracing from FPGA requirements to HDL design sources, implementation, test cases and testbench and test results? What type of output files are needed for traceability? What certification authorities look for when they review the traceability data? Play webinar   
DO-254/CTS Recorded Webinars
Better Coverage in VHDL   
Abstract: Experienced users of VHDL simulation with testbenches appreciate additional layer of safety that Coverage Analysis gives them. But are all kinds of coverage equally beneficial? While Code Coverage is certainly useful, it really verifies quality of the testbench, not the design itself. In this webinar we will show how to improve quality of the design using Property Coverage and Functional Coverage (with help of OS-VVM). Play webinar   
Active-HDL, Riviera-PRO Recorded Webinars
Boost VHDL Development Time with Background Design Rule Checking   
David Clift is an Application Specialist at FirstEDA Limited. David’s electronics engineering career started at GEC Marconi when he joined the company as an R&D engineer in 1984, working on a range of projects including Silicon-on-Sapphire and radiation tolerant ICs. David moved into the EDA industry in 1994. David is Applications Specialist for both Aldec and Sigasi. Hendrik Eeckhaut is founder and CTO at Sigasi. He has a PhD in Computer Science Engineering and did research on artificial intelligence and on FPGA design methodology for scalable video codes. In 2008 he co-founded Sigasi because he believes hardware designers deserve better tools. His mission is to help designers focus on the actual design, and automate away all distractions.  Play webinar   
ALINT-PRO Recorded Webinars
Closed Loop Verification of Large Designs   
Abstract: Modern digital designs reached sizes so huge that traditional, simplistic verification no longer works. Large number of design sources, multiple teams and tools using them, almost infinite stream of results they produce - all those factors create new management challenges. Our webinar will show how verification planning, simulation and regression management can be easily handled using Agnisys and Aldec tools.  Play webinar   
Riviera-PRO Recorded Webinars
Common Testbench Development for Simulation and Prototyping   
Many chip design houses combine both simulation and prototyping processes to achieve the highest level of verification quality of their products. Usually, this process applies for the top-level designs. One of the issues of this approach is the inherent difference between simulation and prototyping environments. In case there is a bug found during prototyping, it is quite difficult to replicate it in the simulation environment. However, there is always a need to do so in order to properly fix the code and verify the fix in simulation. The combination of simulation and prototyping verification stages could be applied not only for top-level design, but for the block-level and IP core verification as well. Complex mission-critical IPs, forward error correction IP, etc., may require much more test stimulus than what simulation provides. In this webinar, we will outline the efficient IP design verification methodology based on the “Common Testbench” approach. The major parts of the Common Testbench could be re-used between simulation and prototyping. While reducing testbench development time, this approach helps to replicate bugs from the prototyping within the simulation environment. The Common Testbench concept will be illustrated using a design example.  Play webinar   
Riviera-PRO, ALINT-PRO, DO-254/CTS Recorded Webinars
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