Event Details View All Recorded Events Date Event Type Location Action Sep 24, 2026 Practical Co-Simulation Techniques with OSVVM Part 3: Introduction to Protocol Verification with Co-Simulation (EU) Time: 4:00 PM - 5:00 PM (CEST) Webinar Overview OSVVM is a powerful open-source VHDL verification methodology and library widely adopted for FPGA and SoC verification. It provides a comprehensive set of capabilities including transaction-based verification, constrained randomization, functional coverage, scoreboards, memory models, reusable testbench architectures, and advanced scripting support across leading simulators such as Aldec’s Active-HDL and Riviera-PRO. Modern FPGA and SoC verification increasingly relies on sophisticated protocol models capable of interacting with RTL simulations at both the transaction and software levels. OSVVM co-simulation enables engineers to extend traditional verification component (VC) architectures by integrating native C and C++ models directly into VHDL-based verification environments. In this, the final webinar in our three-part series, we explore how complex protocol verification components can be constructed using OSVVM co-simulation techniques, using the new PCIe co-simulation VC as a practical case study. The session will examine the architecture and internal design of the PCIe VC, demonstrate how C/C++ protocol models are connected to OSVVM verification environments, and show how similar co-simulation VCs can be developed for other advanced protocols. Attendees will also see a live demonstration of how the PCIe co-simulation VC can be used to drive and verify Altera Cyclone V Hard IP for PCI Express within an OSVVM testbench using Riviera-PRO. Agenda: Introduction to Protocol Verification with Co-Simulation Review of OSVVM Co-Simulation Objectives and Structure of a Co-Simulation VC PCIe C/C++ Model Features PCIe OSVVM VHDL VC Connecting C Models to OSVVM Verification Components Driving Transactions Through the PCIe VC Constructing Reusable Co-Simulation VCs for Complex Protocols Demonstration: Driving the Altera Cyclone V PCIe IP with the PCIe co-simulation VC Conclusions Q&A Webinar Duration: 45 min presentation/live demo 15 min Q&A Presenter BIO Simon Southwell, Freelance Logic and Software Consultant, specializing in co-simulation, HPC and wireless solutionsSimon Southwell, Freelance Logic and Software Consultant, specializing in co-simulation, HPC, and wireless solutions. Engineer with 35 years in Research and Development, with experience in ASIC design, FPGA, and embedded software development. Now spending time contributing IP to the open-source community, and sharing experience and knowledge through writing articles and mentoring undergraduates and junior engineers. Also, currently a collaborator on the OSVVM project, a verification methodology and VHDL library, adding and supporting its co-simulation capabilities. Particular areas of interest include processor systems and sub-systems, system modelling in software, the software/hardware interface, and co-simulation of logic and software. Amongst the many areas of experiences are original logic IP design targeting both ASIC and FPGA, logic verification, HPC (supercomputers), processor systems, networking (802.3 and proprietary), embedded software, co-simulation technology, software modelling of SoC systems, data compression logic, PCIe endpoint design, cellular (3G and 4G), wireless (802.11 and 802.15.4), and more. Joint or sole author on several logic IP-related patents. Webinar Online Register
