Q3-2011 - Aldec™ Design and Verification Newsletter
Free Assertions Training SeminarsAssertions for HDL DesignersThursday, August 18, 2011, 9:00am — 1:00pm Join us for a free, half-day seminar created for hardware designers with practical knowledge of Verilog and/or VHDL. This class is designed to prepare the student for practical usage of assertions in verification tools by explaining basic ideas, introducing key elements of assertions illustrated with simple examples and presenting complete design demonstrating various uses of assertions. Examples will use SystemVerilog Assertions (SVA) and Property Specification Language (PSL) in parallel, giving students more options of further study. Presenter: Jerry Kaczynski, Aldec Research Engineer. UVM Transaction-Level Visual Debugging
Aldec has expanded support for the Universal Verification Methodology (UVM) with comprehensive transaction-level visual debugging. The new capabilities for transactions recording and visualization enable engineers to utilize Riviera-PRO 2011.06 advanced debugging infrastructure without having to manage basic mechanisms for transactions handling. The new UVM 1.0 transaction-level debugging capabilities are immediately available with the latest release of Riviera-PRO 2011.06 at no cost to customers with a valid maintenance contract and SystemVerilog verification support. TechnologySystemVerilog: Who? What? When? Where? SystemVerilog was released as a complete standard in 2009 and will stay with the digital design community whether we like it or not. Quite surprisingly, the only group of people that welcomed SV enthusiastically was the Verification Engineer Guild. Other groups still seem to treat SV with reserve, partially justified by unbearably wide scope of the new language. This presentation explains which areas of SystemVerilog should be implemented by hardware designers. Main topics include Design Subset, Assertions, Verification Subset, Verification Methodologies (OVM/UVM). Cloud-based Verification: Examine the Possibility The advancement of cloud computing is a key development in the latest time and EDA industry is no exception in this domain. Many EDA vendors have been providing different services via clouds but these services are mainly for trying out software or testing the software. At this point there are obvious concerns about security and licensing models. Also the network bandwidth may seem to be the issue for interactive EDA tools. Examine the possibility to use clouds as a technology to manage your verification and simulation using Aldec’s ecosystem. In-Target Testing for Xilinx® Devices for Level A/B DO-254 Compliance Functional verification of the design in real hardware has been a serious undertaking when designing for DO-254 compliance. Designers are presented with significant challenges in meeting chapter 6.2 Verification Process of DO-254 such as requirements traceability, limited controllability/visibility of FPGA I/Os, development of test vectors to match RTL simulation, creation of multiple testing environment for sets of test cases, running the design in the target device “at speed”, and lack of automation in the verification cycle, which all of them ultimately results to a time consuming verification process. Aldec’s DO-254/CTS™ is a certifiable “at-speed” and “in-target” testing environment for complex designs residing in Xilinx devices, and is dedicated to address the true specification of DO-254 via FAA AC 20-152 that complex devices such as FPGAs and PLDs must be tested and verified to requirements at the device level. DO-254/CTS™ consists of a COTS mother board, custom daughter board and proprietary software package designed to provide a single environment to test all FPGA level requirements ideal for Level A/B DO-254 certification. Aldec is Tweeting! Did you know you can get the latest updates from Aldec on Twitter? Simply follow Aldec on Twitter at twitter.com/#!/aldecinc Inc and we will keep you up-to-date on Aldec news and promotions. Click here to follow Aldec on Twitter. Product updates
DVM™ 2011.04 UVM Transaction-Level Visual Debugging
Aldec has expanded support for the Universal Verification Methodology (UVM) with comprehensive transaction-level visual debugging. The new capabilities for transactions recording and visualization enable engineers to utilize Riviera-PRO 2011.06 advanced debugging infrastructure without having to manage basic mechanisms for transactions handling. The new UVM 1.0 transaction-level debugging capabilities are immediately available with the latest release of Riviera-PRO 2011.06 at no cost to customers with a valid maintenance contract and SystemVerilog verification support. UVM Transaction-Level Visual Debugging
Aldec has expanded support for the Universal Verification Methodology (UVM) with comprehensive transaction-level visual debugging. The new capabilities for transactions recording and visualization enable engineers to utilize Riviera-PRO 2011.06 advanced debugging infrastructure without having to manage basic mechanisms for transactions handling. The new UVM 1.0 transaction-level debugging capabilities are immediately available with the latest release of Riviera-PRO 2011.06 at no cost to customers with a valid maintenance contract and SystemVerilog verification support. |
ProductsRiviera-PRO™ 2011.6
Active-HDL™ 8.3 sp1
ALINT™ 2010.10 sp1
HES-DVM™ 2011.10
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