RTL Linting: Proceed with Confidence

Date: Apr 24, 2017
Type: In the News

By Sergei Zaychenko, Aldec Software Product Manager

It is typically performed on the synthesisable Register Transfer Level (RTL) subset of the HDL, be it VHDL or Verilog/SystemVerilog, though it can also be partially applied at the gate level too.

Why lint? Because simulation and synthesis can take a long time, particularly for large gate-count devices, it is worth going into both with the cleanest code possible; thus minimising the risk of having to trace problems back to HDL. Or to put it another way, linting is about securing design quality assurance early on in the design flow.

Linting performs a static analysis of the code, checking it against recognized design rules and best-practice guidelines. It also helps identify problems such as unreachable statements, suboptimal synthesis, simulation versus synthesis mismatches, clock/reset connectivity issues, unsynchronized Clock Domain Crossings (CDCs) as well as looking for obstacles against testability, all of which help reduce the number of synthesis and implementation re-runs.

For the rest of this article, visit EE News Europe.

Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.