Productivity Through Methodology: Aldec Adds UVM Generator to Riviera-PRO™ Plus Updates Its OSVVM and UVVM Libraries

Date: Nov 16, 2021
Type: Release

Henderson, NV – November 16, 2021Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC designs, has added an automatic UVM Generator function to Riviera-PRO™. The addition promises to greatly boost the productivity of Riviera-PRO users taking advantage of the benefits of the Universal Verification Methodology, which contains guidance on the creation and reuse of verification testbenches.


Riviera-PRO’s new function automatically creates the UVM testbench (in SystemVerilog, the language that underpins the methodology) for any given design under test (DUT) written in VHDL or Verilog. It also creates a framework of the UVM code; one that contains comments indicating places that must be manually populated with design-specific code. Along with SystemVerilog source files, the UVM Generator automatically creates the TCL macros for controlling the simulation process. The user can choose a DUT from a library or start a new design from scratch.


The UVM-generated code can also be displayed in Riviera-PRO’s UVM Graph Window, an existing and popular feature with users, for better visualization of the hierarchical UVM components, properties, connections, and dataflow - all of which greatly aid debugging.


Sunil Sahoo, Aldec’s SW Product Manager, comments: “While not the only verification methodology available, UVM is certainly one of the most popular – particularly since its standardization by the IEEE in 2017.”


Aldec has also updated the Open-Source VHDL Verification Methodology (OSVVM, a methodology the company played a significant role in creating) library to version 2021.06 within Riviera-PRO. In addition, the tool’s Universal VHDL Verification Methodology (UVVM) utility (uvvm_util) and VHDL Verification Component Framework (uvvm_vvc_framework) libraries have been updated to version v2021.05.26.


Sahoo concludes: “At Aldec, we’re committed to helping the users of our EDA solutions get as much as possible from their chosen verification methodology, to make them more productive, save time and have increased confidence in their designs.”


Riviera-PRO 2021.10 is now available for download and evaluation.


Boosting productivity: Aldec has added a function to Riviera-PRO™ that automatically creates the UVM testbench (above) for any given design under test.


About Riviera-PRO™

Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. The tool enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.


About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.

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