Advancing VHDL’s Verification Capabilities with VHDL-2019 Protected Types

Date: Mar 29, 2022
Type: Release

The latest release of Aldec’s Active-HDL supports IEEE 1076-2019 protected types, enabling engineers to simplify and abstract the construction of data structures for verification.

Henderson, NV – March 29th, 2022 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, advances VHDL’s verification capabilities  with Active-HDL™, version 13.0.


This latest release introduces support for VHDL-2019 protected types with generics, composites of protected types, pointers to objects of protected types and composition with protected types.


Protected types were introduced in VHDL-2000 to allow the creation of class-like objects (similar to classes in C++), which then later became required for shared variables in VHDL-2002. In VHDL-2019, the capabilities of protected types have been significantly improved to address new use models essential for the creation of complex testbenches that require advanced data structures.


Protected types are a powerful mechanism for creating functional coverage, random test generation, messaging, unified error reporting and verification data structures such as memory models, FIFOs and scoreboards.


Engineers can also use protected types on an entity interface for sharing a single memory among multiple AXI4 memory-mapped external peripherals, ideal for verifying SoC FPGAs used for multi-sensor data aggregation.


“VHDL is still the number one verification language for VHDL-based designs, despite the popularity of SystemVerilog,” comments Louie De Luna, Marketing Director of Aldec. “With VHDL-2019, the language has evolved into a highly capable verification language, thanks to all the efforts of the entire VHDL user community. Unlike other VHDL revisions, VHDL-2019 was requested, ranked, scrutinized, and written by users and balloted by the VHDL community. All tool vendors have a duty to listen to what the design community wants, and we are pleased to respond with enhancements to our products so that users can take full advantage of the power of VHDL-2019.”


Active-HDL 13.0 is now available for download and evaluation.


About Active-HDL

Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.


About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.


Media Contact:          
Amanda Warrilow

Declaration Limited
T: +44 (0)1522 789 000

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