Active-HDL Designer Edition Active-HDL Designer Edition provides FPGA designers with a mixed RTL simulator that includes: industry proven IEEE mixed-language simulation support for VHDL, Verilog® and SystemVerilog (Design), with 2X-plus performance gains over FPGA supplied RTL simulators, encrypted IP support and no limitations on FPGA device size. Top Features Supported Languages Mixed Language Design Support VHDL IEEE 1076 (1987, 1993, 2002 and 2008) Verilog® HDL IEEE 1364 (1995, 2001 and 2005) SystemVerilog IEEE 1800™ (Design) Debugging Interactive Code Execution Tracing Advanced Breakpoint Management Memory Viewer FSM Debug Waveform Viewer Multiple Waveform Windows Waveform Stimulator Encrypted IP SecureIP Support IEEE VHDL and Verilog IP Support Unlimited Design Size Support HDL Design Tools HDL, Text, Block Diagram and State Machine Editor Language assistant with templates and auto-complete Hierarchy Viewer with Configurations Support Macro, Tcl/TK, Perl script support Pre-compiled FPGA Vendor Libraries Project Management Design Flow Manager for All FPGA Vendors Revision Control Interface Workspace and Design Archiving Supported Platforms Windows® 7/Vista/XP/2003 Block Diagram Editor HDL Editor State Diagram Editor Waveform Viewer Download Configuration Pricing North America Europe ROW Customer Reviews "Comtech EF Data engineering has used and compared many other FPGA design entry and simulation tools. Active-HDL far surpasses the competition in tool features and user-friendly interfaces; with a much lower price-tag." Dennis Bennett, Comtech EF Data - USA "Active-HDL simulator enables us to simulate the design many times using a set of stimulus. This leads to improved the quality of the design. Also easy to use waveform viewer help us to debug the design by many features." AISIN SEIKI Co., Ltd. - Japan Order Today!
