Single or Mixed Language

Category : Simulation/Verification

Most ALDEC simulator configurations support mixed (VHDL and Verilog) designs, but single language (VHDL-only or Verilog-only) configurations are also available. The complexity of modern designs frequently requires the use of sources written in multiple languages, so choosing mixed language configuration of your simulator is highly recommended. In addition to plain VHDL and Verilog, mixed language configurations can also support SystemVerilog (Design subset, Assertions, or full language), SystemC and EDIF.

Ask Us a Question
x
Ask Us a Question
x
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.