PSL IEEE 1850, SystemVerilog IEEE 1800™

Category : Assertions and Coverage Tools

Specification of properties and their use in assertions and functional coverage is the essential element of designing modern systems and their verification algorithms. ALDEC tools support three popular languages serving this purpose: Property Specification Language (PSL) and SystemVerilog Assertions (SVA). High-end configuration of ALDEC tools provide assistance while writing properties, using them in assert and cover directives, compiling them, and finally simulating and debugging.

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