Simulation Performance Optimization (Verilog/SystemVerilog, VHDL)

The Verilog RTL & Gate performance optimizer accelerates simulation of all types of Verilog designs, including designs with timing, gate-level designs, and designs with predominantly behavioral code. The optimizer integrates seamlessly with the standard simulation engine and does not require user intervention. By default, the optimizer limits visibility into the design, in exchange for accelerating certain design objects, however, you can change the default behavior and enable read (or read-write) access to accelerated objects, enabling design access by waveform viewer, PLI, and other applications.

VHDL RTL and Vital Optimizations enabled during compilation can result in significant performance improvements. The optimization level during compilation is controlled with the use of various switches in both GUI and batch mode. Additional simulation options are also available to increase performance.