HDL Detailed Design and Verification

HDL development and verification under DO-254 guidelines is a rigorous undertaking and requires special features and capabilities from HDL design and simulation tools. Active-HDL™ or Riviera-PRO™ provides features for graphical design creation, verification, management, and documentation facilitating a flexible and seamless design and verification platform.

HDL Graphical Entry: Block Diagram Editor and State Machine Editor

The Block Diagram Editor is a tool for graphical entry of VHDL, Verilog and EDIF designs. If the HDL design is in large part structural, it may be easier to enter its description graphically as a block diagram, rather than typing hundreds of source code lines.

The State Diagram Editor is a tool designed for the graphical editing of state diagrams of synchronous and asynchronous machines. Drawing a state diagram is an alternative approach to the modeling of a sequential device. Instead of writing the HDL code manually, the designer can enter the description of a logic block as a graphical state diagram.

HDL Code To Graphics Converter

The code to graphics converter is a tool designed for automatic translation of VHDL or Verilog source code into block and state diagrams. It analyzes VHDL, Verilog, or EDIF source files and generates one or more block diagram files depending on the number of design entities, modules, or cells found in the analyzed file. The resulting block diagram files can be automatically attached to a design.

VHDL 2019 Simulation

The latest IEEE Std 1076-2019 standard brings long-awaited improvements and new testbench-related features such as the mode views for composite types and subtypes, inferring signal and variable subtype constraints from initial value, conditional assignments of initial values, conditional subprogram return statement, conditional analysis directives, garbage collection, etc.  Since VHDL is still considered to be safer than Verilog or SystemC, these new testbench-related features together with OSVVM and UVVM VHDL verification libraries are significant enhancements for widely used VHDL 2008 standard. For better compatibility, VHDL 2008 is the default mode for simulation. The user can switch to the newest VHDL 2019 version as well as to the previous 2002 or 1993 versions.

Verilog/SystemVerilog and System C Simulation

Despite most of the DO-254 projects adopt VHDL as the primary design language, SystemVerilog and SystemC become more popular for verification activities. Active-HDL and Riviera-PRO are mixed language simulators with Verilog/SystemVerilog and SystemC support including the latest verification libraries like UVM and OVM.

HDL Debugging and Post-Simulation Debug

Aldec simulators offer a number of features to effectively debug errors and verify the behavior of the design. Active-HDL interactive debugging features include Source Code Tracing, Breakpoints Insertion, Block Diagram Graphical Debugging and State Machine Graphical Debugging. Multiple windows to view simulation results are also available from Active-HDL including List (Delta) Viewer, Watch Window, Processes Window, Waveform Viewer, Dataflow Window and Call Stack Window. Riviera-PRO is the advanced verification platform offering debugging capabilities at different levels of abstraction. The tool features UVM Toolbox, UVM Graph, Class Viewer, Transaction Streams, Plot and Image Viewers for debugging at higher level of abstraction and interactive debugging tools like Code Tracing, Waveform, Dataflow, FSM Window, Coverage, Assertions, Memory Visualization Capabilities for the lower level abstraction.
Post Simulation Debug is a very useful feature that allows debugging a project in the "off-line" mode (without a connection to the simulator). The engineer can perform only one regular simulation to collect the post-simulation data and then analyze the design as many times as needed in the post-simulation mode. Moreover, the engineer can share results of the simulation with others as well as use post-simulation files prepared by anyone on a different computer.

Waveform Viewer/Editor and Tracing Unknown Values

Waveform Viewer is a tool designed to display simulation results in the form of graphical waveforms. During simulation, the simulation kernel outputs waveforms for selected signals and variables in the Waveform Viewer/Editor window. Waveform Viewer/Editor includes a number of useful features like Cursors, Virtual Objects, Transactions, Assertions, Analog Representation, Comparison and Signal Navigator.  Waveforms can be re-applied as test vectors to signals and nets during subsequent simulation runs. Comments and marks can be inserted into the waveforms and then can be printed or exported into a PDF or HTML for documentation purpose.

Unknown and uninitialized values ("x", "w", -, etc.) can be a source of an unexpected behavior on output ports of a tested entity/module. XTrace is a command-line utility that allows detection and reporting of unknown values when they first appear and before they are propagated through a design. It allows stopping the simulation when an unknown value is assigned to any of monitored signals. Corresponding messages about unexpected values, signals and the time when those values were detected are also displayed in the console window.

Assertion Based Verification

Assertions can be used both for detecting errors in a design and for verifying and describing complex sequences of events. Assertions can be used to verify requirements. Assertions can be encapsulated in reusable units with parameterized verification rules, providing the possibility to create independent checkers, specialized for user-defined or universal protocols frequently used in designs. PSL and System Verilog Assertions are supported.

Code Coverage and Toggle Coverage

Code Coverage is a debugging tool that aids the verification process. Code Coverage is also used to support Elemental Analysis, an advanced verification approach described in RTCA/DO-254 Appendix B 3.3.1. Aldec simulators allow verifying source code with the following coverage tools:

Statement Coverage shows execution branches for each HDL statement. This information provides feedback on which parts of the design were verified and which are untested. It also helps to locate dead code.

Branch Coverage collects execution branches for the “if” and “case” constructs as well as VHDL selected and conditional signal assignment statements.

Expression Coverage factorizes logical expressions and monitors them during simulation.

Condition Coverage is an extension of Expression Coverage that monitors and factorizes logical expressions used in conditional statements. This type of coverage monitors expressions that occur as a condition within constructs such as “if then”, “while”, and so on.

FSM Coverage allows the user to identify not visited states and not evaluated transitions.

Path Coverage collects information about the program execution and analyzes whether all combinations of program sequences (program paths) are verified by a testbench. A program path is a sequence of statement executions performed in a particular order. The tool also collects information about the order of how the consecutive statements are executed, the branches that are examined, and how logical conditions evaluated during simulation.

Toggle Coverage is a program that measures a design activity within terms of changes of signal logic values. Toggle Coverage creates a report that provides information: whether monitored signals were initialized, whether monitored signals experienced rising and/or falling edges, and the number of rising and falling edges during the simulation session. The report helps verify the quality of stimulus and locate non-active structures of the design. Signals that were not initialized during the simulation or are not exercised properly by the testbench can be easily identified.

Source Revision Control and Design Documentation Capabilities

Source Revision Control allows operating on subsequent versions and revisions of design source files directly from the HDL simulator environment. In such an environment, it is possible to track the changes in a design and view differences between subsequent versions of files. The Source Revision Control system also makes team work easier as it allows a group of designers to work on the same project. Once the files are archived in a repository, they are available to other team members. Additionally, all changes that have been made to any file are saved with a full history, so you can recover any version of any file at any time. Members of your group can see the latest version of any project, make changes, and save a new version in the Source Revision Control system database.

Design documentation for DO-254 certification is a necessity. Active-HDL consists of powerful documentation features allowing the engineer to create a textual or graphical representation of the workspace or design in HTML or PDF format. All design elements such as design files, waveforms, block diagrams and attached documents can be exported to HTML or PDF documents which can be controlled by various options in the wizard. The resulting documents always preserve the hierarchy of the design which provides easy navigation in complex designs. Export to vector graphics capability maintains the high resolution of schematic files in the generated document.

Integration with 3rd Party Synthesis and P&R Tools

Active-HDL's Design Flow Manager provides seamless interfaces with 3rd party synthesis and P&R tools and facilitating a unique platform that can be used throughout the FPGA design flow.

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