VUnit VUnit is an open-source unit testing framework for VHDL/SystemVerilog, which provides the necessary functionality for continuous and automated unit testing of HDL (Hardware Description Language) code. Rather than replacing traditional testing methods, VUnit complements them by promoting a "test early and often" approach through automation. VUnit supports Riviera-PRO and Active-HDL. VUnit reduces the overhead of testing by supporting automatic discovery of testbenches and compilation order as well as including libraries for common verification tasks. It enhances development speed by supporting incremental compilation and by enabling large testbenches to be split up into smaller independent tests. It increases the quality of projects by enabling large regression suites to be run on a continuous integration server. VUnit does not require its users to follow a specific verification methodology. The advantages of VUnit can be experienced whether tests are written at the beginning or end of the development process, whether they are extensive top-level tests or quick unit tests, and whether directed or constrained random testing is used. Many projects mix these two approaches to meet different testing requirements. VUnit has been successfully utilized in production settings where numerous tests run for hours on high-performance multi-core machines, as well as in smaller open-source projects where only a small package is tested in a matter of seconds. Primary Use Case VUnit is designed to automate and streamline HDL testing for VHDL and SystemVerilog, making it easier to conduct unit tests and verify designs. This tool helps developers ensure high-quality HDL code through early and automated testing practices. Benefits Scriptable API and command line support, with GUI mode for debugging Automatic scanning for tests and file dependencies enables incremental compilation and execution of test suites. Python test runner supports parallel testing, test independence, and recovery from fatal errors Traceability through JSON export, test attributes, and JUnit report output for CI integration Built-in HDL utility libraries: Run library providing functionality for declaring multiple test cases within HDL testbenches. Assertion checkers that extends VHDL built-in support (assert). Logging framework supporting display and file output, different log levels, visibility settings of levels and design hierarchy, output formatting and multiple loggers. Communication library providing a high-level communication mechanism. Verification Components library providing verification components (VCs) for interfaces such as AXI, Avalon or Wishbone. Third-party support for: OSVVM JSON-for-VHDL VUnit blogs Introduction to VUnit blog Speeding up Simulation with VUnit for Parallel Testing blog Navigating VUnit: A Practical Guide to Modyfing Testing Approaches blog Additional links https://vunit.github.io/ https://github.com/VUnit/vunit
