Tutorials Search in Resources Articles Manuals -OR- All Products Active-HDL Riviera-PRO ALINT-PRO HES-DVM HES Proto-AXI HES™ Boards RTAX/RTSX Adaptor Boards HES-DVM Proto Cloud Edition TySOM™ EDK Spec-TRACER DO-254/CTS All Documents Application Notes Manual Demonstration Videos FAQ Recorded Webinars Tutorials White Papers Technical Specification Case Studies All Categories Coverage 3rd Party Integration Design Entry, Documentation Simulation, Debugging Design Management, Libraries Advanced Verification Assertions and Functional Coverage RTL Simulation & Verification HDL Languages Encryption Military & Aerospace Verification Design Rule Checking Design Hardware Emulation Solutions Encryption Design HDL Languages RTL Simulation & Verification Assertions and Functional Coverage Advanced Verification Design Rule Checking Military & Aerospace Verification Hardware Emulation Solutions Tutorials Prototyping High-Level Synthesis Embedded Embedded Embedded High Performance Computer SoC & ASIC Prototyping Reset Results Name Products Type Action Advanced Dataflow Learn how to use Advanced Dataflow in Riviera-PRO Riviera-PRO Tutorials Assertions Learn how to use Assertions in Riviera-PRO Riviera-PRO Tutorials Basic OpenCV Image Processing Tutorial TySOM This document will show the process of creating software applications for TySOM development boards by utilizing OpenCV to build an image processing application. OpenCV is an open source computer vision software library that provides the algorithms and functions used for image and video processing. TySOM™ EDK Tutorials Basic UART Interface Tutorial TySOM-1-7Z030 In this tutorial, you will learn how to use UART to interface the TySOM-1-7Z030 board with other systems. The UART interface enables us to view serial output from the board which can be useful for monitoring. This project has both a hardware and software part. TySOM-1-7Z030, TySOM™ EDK Tutorials Building and Configuring a Linux OS using the Linaro The Linux operating system is a very popular operating system for embedded applications. Many modern systems including IoT gateways use the Linux OS because of its versatility and support for multiple architectures. The Aldec TySOM platform, which based on the Xilinx Zynq SoC with ARM Cortex processor, can be utilized as an IoT Gateway system. This document describes the process for building an embedded Linux OS for the Aldec TySOM platform using the Analog Devices Linux kernel and Linaro sources for creating Linux File System. TySOM™ EDK Tutorials Building and Configuring a Linux OS using the Yocto Project - TySOM-1-7Z030 This document describes the process for building an embedded Linux OS for the Aldec TySOM platform using the Yocto project, an open source collaboration project for creating custom Linux-based systems. TySOM-1-7Z030, TySOM™ EDK Tutorials Code Coverage Learn how to use Code Coverage in Riviera-PRO Riviera-PRO Tutorials Connecting Leopard camera to TySOM-3-Zu7EV board using FMC connector This demo design uses TySOM-3-ZU7EV board to capture the LI_IMX274MIPI camera 4K video through the FMC HPC connector on the board and show it on a screen. LI-IMX274MIPI-FMC is a high-resolution digital camera board. It incorporates a Sony 1/2.5" CMOS digital image sensor with an active imaging pixel array of 3864H x2196V. TySOM™ EDK Tutorials Course 01 - Getting Started With Active-HDL This tutorial provides instructions for using the basic features of the Active-HDL simulator. Active-HDL is an integrated environment designed for development and verification of VHDL, Verilog, System Verilog, EDIF, and System C based designs. In this tutorial we use a Sample VHDL design called PressController from the Active-HDL installation to perform design entry and simulation. Active-HDL Tutorials Course 02 - Running Simulation in the Batch Mode This document describes running an HDL simulation using Active-HDL in the batch mode. Active-HDL Tutorials Course 03 - Running Simulation in GUI Mode This document describes running an HDL simulation using Active-HDL in the GUI mode. Active-HDL Tutorials Course 04 - Library Management This document describes managing libraries in Active-HDL. Active-HDL Tutorials Course 05 - VHDL Performance Optimizations This tutorial explains what compilation and simulation options (switches) must be used to achieve the ultimate VHDL simulation performance. Active-HDL Tutorials Course 06 - Verilog Performance Optimizations This tutorial explains what compilation and simulation options (switches) must be used to achieve the ultimate Verilog simulation performance. Active-HDL Tutorials Course 07 - Waveform Viewer Active-HDL stores simulation results in a signal database file for easier design management. Active-HDL Tutorials Course 08 - Advanced Dataflow The Advanced Dataflow window is a tool that allows you to explore the connectivity of a simulated design and analyze dataflow among instances, concurrent statements, VHDL signals and Verilog nets and variables. Values in the design logic can be traced back to their origin, and forward, to the design outputs. Active-HDL Tutorials Course 09 - HDE Based Debugging An HDL code breakpoint can be set in HDL source files that are VHDL, Verilog, and SystemVerilog. A breakpoint can also be set in OVA and PSL code, for example in lines that contain assert or cover statements. Active-HDL Tutorials Course 10 - Debugging Tools Active-HDL users have access o a rich set of debugging tools that enables quick ways to detect and diagnose design issues. Active-HDL Tutorials Course 11 - XTrace XTrace tool creates a report with information on unknown values in the simulated model. Active-HDL Tutorials Course 12 - Code Coverage (Statement, Branch, Toggle, Expression Coverage) Code Coverage aids the verification process by providing information in details whether and how the design is verified or which parts of the design are still untested. Active-HDL Tutorials 95 results (page 2/5)
