Play WebinarTitle: Design Rule Checking (DRC) for Common SystemVerilog Design MistakesDescription: Due to the size and complexity of current hardware design, design verification tasks can become increasingly complex and lengthy. Recent advancements in hardware design have focused on cleaning up design code as much as possible prior to entering the design verification stage. Unfortunately, such design code cleanup performed during relatively short time may significantly reduce overall design verification time and effort. As SystemVerilog design constructs gain popularity among hardware designers, it is increasingly important to assist designers with Systemverilog design code verification and cleanup. ALINT-PRO™ is a design verification solution for SystemVerilog, Verilog and VHDL RTL code. It is able to statically verify and cleanup the code far beyond compiler-level checks. It is capable of statically verifying most of the popular SystemVerilog design constructs, uncovering some of critical design issues early in the design cycle. Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
