Play WebinarTitle: FPGA Design Verification in a Nutshell (Part 1) Verification PlanningDescription: As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop homegrown verification processes. In this three-part webinar series, we will discuss design verification with a focus on creating an advanced simulation-based verification process; from verification planning and team organization, and moving on to regression setup, functional coverage collection, randomization and ‘verification done’ definitions. We will also show you how to develop simple yet powerful and reusable testbenches using Verilog and SystemVerilog constructs and how to functionally verify designs in the most efficient way. In part 1 of this webinar series, we will provide an overview of advanced simulation-based verification process and outline the differences between ASIC and FPGA-centric verification processes. Then, we will show you how to develop a verification plan; describing WHAT to verify and HOW to verify it. Finally, we will talk about design verification of highly configurable design and IP blocks.Signing up for an account is easy. With an Aldec account you'll have easy, one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. Simply provide your corporate e-mail address below - all account requests are verified and confirmed within 48 hours. If you already have an Aldec account, please Sign In below to download the file. Register Sign In
