Play Webinar

Title: Turbocharge your FPGA Simulation Workflows Part 3: High-Performance RTL Simulation Workflow with Libero and Active-HDL

Description: In the concluding part of this three-part webinar series, we will show how to simulate a Microchip design example. We will generate a design example from Libero SoC and simulate it using Active-HDL as the default simulator. We will discuss various tips that you can use to optimize compilation and simulation run times. The tips will be categorized from zero-cost effort to high-cost effort and, depending on your budget/resource constraints, you will have a path to speed up your simulation by a huge factor. We will turn on Profiler so that you can determine the bottlenecks in your design/testbench and we will perform debugging using Breakpoints, Xtrace, Drivers/Readers and Advanced Dataflow. Agenda: > Workflow with Libero SoC and Active-HDL > Tips on how to optimize simulation performance > Performance bottleneck analysis with Design Profiler > Breakpoints, Xtrace and Advanced Dataflow, Drivers and Readers > Live Demo > Q&A

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