Aldec Design and Verification Blog
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One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain....

The latest crop of FPGA devices are enormous when compared to ASICs that were built not that long ago. Verifying these ASICs required detailed plans, multiple tools, and sometimes special languages....

Just in time for Halloween, Aldec has released a popular past webinar Don’t be Afraid of UVM for Hardware Designers on YouTube. Designers are usually very busy doing their work and have little time left for experimentation...

Place & Route implementation can sometimes feel like it takes forever. Consider some of these common scenarios: ● After working overtime to create an emulation build for all emulation users, your manager brings you some...

In James Bond movies, Agent 007 has some awesome gadgets but never listens to Q’s instruction on how to use them properly. I’ve often wondered what it would be like if Bond actually did learn about the various features of his tools...