Case Studies Search in Resources Articles Manuals -OR- All Products Active-HDL Riviera-PRO ALINT-PRO HES-DVM HES Proto-AXI HES™ Boards RTAX/RTSX Adaptor Boards HES-DVM Proto Cloud Edition TySOM™ EDK Spec-TRACER DO-254/CTS All Documents Application Notes Manual Demonstration Videos FAQ Recorded Webinars Tutorials White Papers Technical Specification Case Studies All Categories Coverage 3rd Party Integration Design Entry, Documentation Simulation, Debugging Design Management, Libraries Advanced Verification Assertions and Functional Coverage RTL Simulation & Verification HDL Languages Encryption Military & Aerospace Verification Design Rule Checking Design Hardware Emulation Solutions Encryption Design HDL Languages RTL Simulation & Verification Assertions and Functional Coverage Advanced Verification Design Rule Checking Military & Aerospace Verification Hardware Emulation Solutions Tutorials Prototyping High-Level Synthesis Embedded Embedded Embedded High Performance Computer SoC & ASIC Prototyping Reset Results Name Products Type Action Thales Case Study: Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance We recently helped Thales evaluate the use of transaction level modeling for FPGA designs that use high-speed bus interfaces. We also helped our customer apply high-level test scenarios, verify 100% FPGA-level requirements by test and shorten their overall verification times. In this case study, you’ll hear from Thales on the verification challenges they were facing and how, with support from us, some great solutions we’re developed; all during a proof-of-concept project that has the potential to change the way all PCIe-based FPGA safety-critical designs are verified. DO-254/CTS Case Studies 1 result
