Acceleration-Ready UVM

We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look. But how do you combine the two? How do you run a UVM-based constrained random verification environment alongside an emulator and get reasonable execution speed?

Many vendors have solutions, including Aldec with their HES-DVM™ emulator. Their solution is based on the Accellera SCE-MI standard, and in particular on SV-Connect, which is a function-based interface that uses the SystemVerilog DPI (Direct Programming Interface) to pass information between the host and the emulator. You partition your UVM drivers and monitors into two parts, a small proxy that remains on the host and a synthesizable implementation that goes into the emulator. That way, all of the low-level timing detail is removed from the UVM code running on the host and is placed in the emulator, where it belongs. The communication between the host and the emulator can be optimized to avoid the emulator being stalled while waiting for the slower UVM simulation running on the host.

You can start investigating the UVM coding style needed to run alongside an emulator right now by taking advantage of Doulos’ Easier UVM Code Generator running on EDA Playground. We provide a specific example that demonstrates the use of split transactors, which you can run live over the web.

You can find out more by attending a free webinar, Acceleration-Ready UVM, which will run in multiple time zones on Wednesday 13^th April 2016. Click here to register.