Riviera-PRO 2013.06 Enables Class Hierarchy Visualization

For UVM-Based Verification Environments

Mariusz Grabowski, FPGA Design and Verification Engineer
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As Product Manager, I am especially pleased with the level of increased verification productivity we are delivering in the most recent release, Riviera-PRO™ 2013.06.  In particular, verification teams will find the new class hierarchy visualization for UVM-based verification environments will make it easier to deploy class-based Testbench environments. Here’s an excerpt from the recent press release:


“The new 'Classes' window available with this release provides essential information about the operation of verification environments that are based on the object-oriented library and dynamic data types.”


As the structure of UVM is defined by the hierarchy of SystemVerilog classes, it is essential that a verification platform provides proper insight into the object-oriented environments, while remaining consistent with standard source code and waveform viewing tools widely used by RTL design and verification engineers. Riviera-PRO 2013.06 presents SystemVerilog classes in the form of a hierarchical tree view, integrated with the rest of the IDE for easy cross-probing and navigation, and providing indication of class inheritance, methods, properties, and other important attributes.


You can see the rest of this press release in the Aldec Newsroom.

Here are a few more highlights from the latest release of Riviera-PRO:


Simulation. We were able to boost Verilog, SystemVerilog, VHDL, and mixed-language simulation performance with this release based on some of our larger customers' design environments. We achieved +10% average simulation performance increase vs. the previous version of Riviera-PRO (2013.02). Now a simulation run that used to take some 10 hours completes in about 9.


Even more remarkable speedups were achieved in simulations with code coverage (statement, expression, etc.). With Riviera-PRO 2013.06, you should be able to shorten your simulation sessions with coverage enabled by a whopping 2-3X ratio. Even more good news for UVM users, with this release we have rewritten our constraint solver from the ground up, making it substantially more efficient and able to handle the very complex constraints for random stimuli generation that some of our customers are coming up with.


Debugging. Of course we have the new Classes window, which, combined with the other debugging tools in Riviera-PRO's IDE and the latest versions of the UVM library, provides a great tool for building sophisticated class-based testbenches.


We have also implemented many improvements based on feedback from our customers on new functionality that was introduced in the last few releases. As such, there are many new functions for building virtual expressions in the waveform and observing complex relationships between different objects. For example, Plot window, which was introduced with the previous release and has been improved for image-based plots visualization making it more convenient for our image processing customers to use and source-level debugging which enables you locate objects in hierarchy view directly from the source code.


We also support Windows 8 now, which probably is not a huge deal given the popularity of this new OS from Microsoft. Regardless, we have a workaround for one nasty bug in Qt which prevented our waveform from looking pretty. Now it's all good, so if you are thinking to buy one of those new laptops with Windows 8 preinstalled, you can rest assured that your latest version Riviera-PRO will work just fine.


For more details, you can download the Riviera-PRO 2013.06 What's New presentation. For a complete list of new features and enhancements, view the Riviera-PRO 2013.06 Release Notes.

Mariusz Grabowski is an FPGA Design and Verification Engineer at Aldec. He works in the field of verification for DO-254 compliance as well as developing digital processing systems. He is proficient in digital design and verification, using hardware description languages such as Verilog/SystemVerilog and VHDL, and the use of verification methodologies such as UVM.

Mariusz is a student at the AGH University of Science and Technology in Krakow, Poland. He also gains practical experience in the AVADER Scientific Group (where he designs novel vision systems on FPGAs) and in the Integra Scientific Group (where he acquires knowledge about microprocessor systems and electronics).

  • Products:
  • Riviera-PRO
  • Advanced Verification


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