Legacy Schematic Designs Giving you a Headache?

Retargeting Legacy Designs for New Technology

Deep Shah, Corporate Applications Engineer
Like(3)  Comments  (3)

Digital design has come a long way since its inception from drawing schematic on paper, to CAD tools which can be used to draw schematics, and to today’s most popular (and efficient) process of describing designs through HDLs.


I recently encountered a customer with a legacy design developed in block diagram format. If he hadn’t been an Aldec customer, he might have been stuck. Fortunately,  Aldec Active-HDL™ provides utilities for importing legacy schematic based designs from Xilinx® Foundation Series, ViewLogic™, ViewDraw™, Active-CAD™ or any schematic tools that can output an EDIF netlist.


A common problem

This particular customer had projects in a legacy Active-CAD format, pdf. (Today, when you hear pdf you may think ‘document’, but there was a time when block diagram projects were in pdf format.) Now, on top of these older formats, the customer had designs targeted for legacy FPGA devices like Xilinx Virtex®-2. This was a real problem, as Xilinx itself has discontinued this device along with any support for it. Therefore, there was no library (which contains all gates and blocks used to create these designs) for this device.


A complex challenge

Imagine if you were in this engineer’s shoes, required to redesign a legacy design while addressing functionality issues to match today’s standards. As we well know, a 20 year old design may as well be 100 years old given how rapidly this industry advances. Issues to address might include changing frequency, adding memory, adding functionality such as Wi-Fi or internet capabilities, and most importantly changing targeted devices from discontinued, small and slow devices to newer, smarter, faster, and larger ones.


This would be a tremendous challenge to anyone, even yourself (fine engineer that you are), as it involves addressing multi-year upgrades in multiple aspects of the design. To make things worse, perhaps you are a  new employee, and the design in question was created 10, 15, or even 20 years ago. This usually means a lot of manual work which can go for months in order to bring the designs up to date with newer technology.


Relief from the pain

If you were the unfortunate designer facing this daunting task, you might be wishing there were a tool on the market that might solve this problem for you. Fortunately, the actual designer that I recently worked with to solve this problem was an Active-HDL user. This solution offers the capability to not only deal with these old-fashioned designs, but to bring them into a new environment - and make them smarter.


Not to paint too rosy a picture, naturally there will still be manual steps involved. Active-HDL automates approximately 60%-65% of work (in some cases up to 80%) but not 100%. Fortunately, once again there is good news in that you are not on your own with these steps. Aldec has prepared guidelines and instructions on how to perform remaining manual work, and we are always available to support our users through these transitions.  The steps required to import legacy designs into Active-HDL are outlined below.


Importing a Legacy Design into Active-HDL


A legacy pdf project which was developed in Viewlogic or Active-CAD schematic editors may be easily imported to the current Active-HDL environment, and then converted to HDL.


Retargeting to newer FPGA devices

Active-HDL provides legacy schematic libraries and newer devices library so that old devices can be retargeted to newer ones.


This action will change all Virtex-2 devices (gates and blocks like multiplexers etc.) to Virtex-6 devices. If a significant time difference between two devices exists, the tool may not be able to automatically replace them, and manual work will be required.


Retargeting to HDL from EDIF

Using HDLs for daily design activity is strongly recommended. All EDA tools support both HDLs, whether VHDL or Verilog. Synthesis engines also support both languages. All functional simulation tools and synthesis tools will continue to support these languages for at least the next decade so better create and maintain all aspects of design in HDLs.


Then, if devices changes or libraries vanish, it is a simple matter of editing the code to make things work compared to schematic based designs. To change functionality, again simply add or remove lines from the code.


Active-HDL is full blown simulation tool which provides this conversion, while supporting HDLs so users can simulate a newly converted design and check its behavior in waveform viewer. In Active-HDL, it is also possible to change the target language from EDIF to VHDL/Verilog.



Click here to learn more about Aldec Active-HDL, including free evaluation download, resources, and training.



As a Corporate Applications Engineer, Deep leverages Aldec’s leading FPGA design entry and simulation tools to solve customer problems and also provides support during product evaluations. His practical engineering experience includes areas in solid state electronics, digital designing and functional verification. Deep received his B. Tech. in Instrumentation & Control Engineering from Nirma University, India in 2007 and M.S in Computer Engineering from Polytechnic Institute of NYU, New York in 2009.

  • Products:
  • Active-HDL
  • FPGA Design Simulation


I have a problem simulating block diagram, the output of the blocks does not change, just a "U" value is observed, can you help?
Jose Antonio J. over 8 years
Hello Jose. So our Support Team can assist, can you please open a support case here: https://www.aldec.com/en/support/customer_portal/cases/new
Christina T. over 8 years
Hello Jose. So our Support Team can assist, can you please open a support case here: https://www.aldec.com/en/support/customer_portal/cases/new
Christina T. over 8 years
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