Event Details View All Recorded Events Date Event Type Location Action Jul 01 - 03, 2025 FPGA Conference Europe (EU): Aldec Seminar - Why VUnit? | Language / Debug / Verification In the realms of HDL code verification, where precision and efficiency are crucial, a great hero has emerged; VUnit. This open-source framework for VHDL/SystemVerilog has been making waves in the industry, offering a unique approach to verification that promises to revolutionize the way we test and validate HDL code. In this seminar, we will explore how VUnit integrates seamlessly with comercial simulator, we guide you through creating a project from scratch, and demonstrate how to run multi-threaded unit testing, how to modify each testing approach to enhance your unit testing with VUnit even further, making it more intuitive to use. We propose solutions of integrate VUnit with other flows. Speaker: Michal Pacula, Aldec, Inc. Date: Wednesday, 2 July 2025 Time: 3:05 - 3:45 pm Industry Event Munich, Germany More Info
