White Papers

Simulation-to-Synthesis mismatch issues may cause malfunctions of physical devices. Even for functionally flawless RTL simulations, their physical implementation may contain critical design bugs. RTL Linting is the only way to locate and fix Simulation-to-Synthesis mismatch issues. The following article presents typical simulation-to-synthesis mismatch issues, illustrated by simple examples. For each one of described issues, the Lint checks are identified and explained.

With the latest FPGA technology advancements and release of large-scale FPGA devices, design teams are facing more challenges than ever in producing high quality HDL code. In order to save time during Functional Verification and Implementation stages, it becomes increasingly important to ensure the quality of design starting from the very early stages of the design process. In an ASIC design flow, a Lint tool (sometime referred to as Design Rule Checkers) ensures early-stage design quality, and maintaining this quality throughout the project lifecycle.

Abstract: Debugging a design during emulation with a high level of visibility can be a challenge. This paper presents Aldec’s solution to this problem; a debugging environment for SCE-MI co-emulation that provides 100% signal visibility of the design running in an FPGA-based emulator. Debug probes captured intelligently from emulator retain original signals names and hierarchy paths to provide true RTL view of design in emulation.

Abstract: Modern ASIC and FPGA designs can usually be treated as complete systems, not just electronic circuits. Design and verification of those systems typically requires the use of transaction-level descriptions, so enhanced support for transactions in verification tools is critical. This paper describes basic transaction related terms and the new transaction recording and visualization solution available in Riviera-PRO™ simulator.

Floating-point arithmetic becomes a widely used format in digital system design. For example, DSP applications often demand high precision while operating with large dynamic ranges. The IEEE 754™-2008 floating-point arithmetic standard fulfills this criterion but it might be extremely hard to comprehend and use. This document discusses challenges associated with debugging floating-point arithmetic designs and explains how to tackle them using the tools available with your floating-point aware IDE.

Abstract: The first decade of the 21st century brought tremendous growth of the size of typical digital design, triggering growing demands for faster, safer and more thorough verification. In response to those demands, many new flavors of verification were invented and implemented in the tools, making engineers face difficult choices. This paper gives detailed overview of currently available verification methodologies suitable for large designs and shows how Aldec tools can help in their implementation.

Abstract: Modern digital designs reach the scale of complete systems and require support of Constrained Random Test and Functional Coverage in verification. Although VHDL does not have built-in, direct support for those methodologies, there are neat solutions that allow their quick implementation in your testbench.

Abstract: The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.

SystemVerilog interfaces offer some very interesting features for both hardware designers and verification engineers. Unfortunately, they are also one of the most misunderstood SV constructs. This document tries to explain interfaces, paying special attention to the virtual interface concept used in popular UVM library.

The most commonly used approach to analyzing objects in an HDL design, is based on the well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient for applications such as image processing, digital filter design, embedded system design, and others. This document presents Plot, a new solution for a graph-based analysis of HDL objects, correlations between them, and a number of practical applications for it.

Modern RF system designs require extensive digital signal processing and flexibility to fulfill the current and coming standards. Systematically growing set of functions implemented on SoC pushes system architects and hardware designers to look for methodologies, which would enable efficient co-design and co-verification. In this paper, we will be discussing the challenges associated with simulating multirate system-level designs that include multiple digital blocks.

ADAS is an essential step between initial DA (Driver Assistance) systems and fully autonomous cars capable of driving without human guidance. Aldec provides an FPGA-based development platform powered by Xilinx Zynq-7000 SoC/FPGA heterogeneous technology, as well as a set of ADAS-class reference designs for rapid development of current and next-generation ADAS solutions for the automotive market.