Aldec Design and Verification Blog Trending Articles FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM The Convergence of Emulation and Prototyping Development of real-time SDR systems with Aldec HES Performing cross spectrum video processing on a TySOM-3 board How does the Mars Perseverance rover benefit from FPGAs as the main processing units? All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Linting RISC-V designs with ALINT-PRO As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions, and their flexibility, creates a problem when choosing the most reliable and robust solution from a number of contenders.... Tags:ASIC,FPGA,HDL,Verification,Verilog,Design,Digital,IP,Linting,SoC,SystemVerilog Like(2) Comments (0) Read more The Power of PCIe in Performance-based FPGA World Understanding High speed serial data transfer In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?... Tags:Aceleration,ASIC,Co-simulation,Documentation,Embedded,Emulation,FPGA,FPGA Simulation,Hardware,HDL,IP,Prototyping,Simulation,SoC,Validation,Verification,Xilinx Like(3) Comments (0) Read more Why I see C in SCE-MI A Hardware Emulation Guide for Non-C Designers The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”?... Tags:IP Like(5) Comments (0) Read more Transitioning to Advanced Verification Techniques for FPGAs – Catch-22? A Guest Blog by TVS Founder and CEO, Dr. Mike Bartley Many FPGA designers find themselves in a catch-22: they recognise that their designs are becoming too complex for their current verification strategies BUT adopting advanced verification techniques (such as the Universal Verification Methodology – UVM) is... Tags:FPGA,Randomization,Verification,Coverage,Digital,IP,Simulation,Verilog,VHDL Like(2) Comments (0) Read more
