Aldec Design and Verification Blog

As the open-source RISC-V instruction set architecture (ISA) continues to gain momentum, the growing number of RISC-V design solutions, and their flexibility, creates a problem when choosing the most reliable and robust solution from a number of contenders....

In today's world, when the entire computing industry is talking about high-performance and high-speed applications using FPGAs, just what are the factors that can assure such performance and speed?...

The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”?...

Many FPGA designers find themselves in a catch-22: they recognise that their designs are becoming too complex for their current verification strategies BUT adopting advanced verification techniques (such as the Universal Verification Methodology – UVM) is...