Aldec Design and Verification Blog Trending Articles Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM The Convergence of Emulation and Prototyping All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it,... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(4) Comments (0) Read more Understanding the inner workings of UVM - Part 3 UVM Basics Part 3 of 3 In this blog, I am going to discuss different phases that UVM follows. The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL,... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(2) Comments (3) Read more Understanding the inner workings of UVM - Part 2 UVM Basics Part 2 of 3 In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(3) Comments (0) Read more Understanding the inner workings of UVM UVM Basics Part 1 of 3 We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount... Tags:ASIC,Co-simulation,Coverage,Debugging,Documentation,FPGA,OS-VVM,UVM,Verification Like(3) Comments (0) Read more Beer, Cars, and Verification My thoughts after DVCon Europe As I write this, I am visiting the Aldec corporate office in the US on the day following their historical presidential election. It’s been a busy travel season for this product manager, and only a few weeks ago I was at DVCon Europe in Munich - the city of pork knuckles, beer... and of course, cars. ... Tags:Auto,Embedded,OS-VVM,SoC,UVM,VHDL Like(5) Comments (0) Read more The 80s music at DAC was my idea. You're welcome. DAC Chats to be presented live online If you attended the Monday Night Reception at DAC 2014, you were greeted with a blast of 80s pop music. If you then said to yourself, “I’d like to meet the genius behind that idea” - that would be me. A few weeks before DAC... Tags:Embedded,OS-VVM,safety-critical,Training,UVM,Verification Like(3) Comments (0) Read more My First Example with OS-VVM CoveragePkg A Guest Blog from Alex Grove of FirstEDA Here in Europe, I recently had the opportunity to work with Jim Lewis, OS-VVM Chief Architect and IEEE 1076 Working Group Chair, on the first Advanced VHDL Testbenches & Verification training course.... Tags:Coverage,Design,FPGA,OS-VVM,Randomization,Verification,VHDL Like(3) Comments (1) Read more Why Randomize? Guest Blog with Jim Lewis, VHDL Training Expert at SynthWorks After presenting a conference paper on how to do OSVVM-style constrained random and intelligent coverage (randomization based on functional coverage holes), I received a great question, "Why Randomize?"... Tags:Coverage,OS-VVM,Randomization,VHDL Like(2) Comments (0) Read more 90’s Kid Active-HDL Celebrates Sweet 16 Serving FPGA Designers as the tool of choice since, like, forever As the proud Product Manager of Aldec’s FPGA Design Simulation solution, I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997.... Tags:Assertions,Co-simulation,Coverage,Debugging,Design,Digital,Documentation,FPGA,HDL,IEEE,Matlab,OS-VVM,Simulation,standards,university,Verification,Verilog,VHDL,Xilinx Like(2) Comments (2) Read more
