« Prev | Next » Simulating ALTERA NIOS II Embedded Processor Designs in Active-HDL This application note describes how to simulate ALTERA NIOS II Embedded Processor Designs in Active-HDL. This is based on the “Board Diagnostics” sample design taken from Eclipse IDE for C/C++ Developers software, but basic flow should remain the same for other designs as well. Tool Requirements This application note assumes that users have installed the following software and have prior experience using them. Altera Quartus II 10.1 or later Altera Quartus II 10.1 or later NIOS II EDS 9.0 or later Active-HDL 8.3 or later Setting up the design Create an empty folder “TEMP” in the “C:\” root directory, go to “computer >properties> advanced system settings”, and click on the Environment Variables button and set the System variables TEMP and TMP to the empty folder as shown. Figure 1: Environment setup Click on the path System variable as shown below, check it for double semi-colons “;;” and replace all “;;” with a single semi-colon“;” in the path statement. Reboot or restart the computer. Figure 2: Path Integrity Check Open Quartus II software From the File menu, select Open project Select the appropriate “.qpf” file from the project directory and click Open, a design sample is shown below. Figure 3: Quartus II Configuration Controller Project SOPC Builder simulation settings After the project is loaded in to Quartus II Software, go to menu Tools and click on SOPC Builder and check all connections in the chosen design. See the sample screen below. Figure 4: clk_0 clk_reset connection Check to ensure that no errors exist as the example shown below. Read all Warnings and Information items to determine their overall affect on the chosen design. Figure 5: Design Status Window Simulation File Generation Click Next to enable the simulation file generation On the System Generation tab, turn on the Simulation. Create project simulator files option Figure 6: System generation settings Click Generate. Click Save when prompted to save changes Figure 7: Generate simulation files tab Figure 8: Generation Complete Building software tools and generating memory initialization file To create and build the software project in Eclipse perform the following steps: Open NIOS II Software Build Tools for Eclipse Go to File>New>>Project> Select NIOS II Application and BSP from Template and click on Next Figure 9: Create new project in NIOS II IDE In the next window, use the browser to find the SOPC Information File Name and click Open. Figure 10: Select SOPC Info File Select the Board Diagnostics Project template and name the project “BD_big_stack”. Click “Next”. Alert: The HAL BSP does not support a Memory Management Unit (MMU), therefore to use one of the Eclipse NIOS II Software Examples the MMU needs to be eliminated from the design. Figure 11: New project settings Select the Create a new BSP project based ......and match the settings below. Click “Finish”. Wait for the status window to complete. Figure 12: BSP Creation Observe the project creation and status window output shown below. *** Clean-only build of configuration Nios II for project BD_big_stack **** make clean [BD_big_stack clean complete] Select the project and right click>select Properties>>Project References and match the settings shown below. Click OK. Figure 13: Project References Select the “BD_big_stack” project and right click>select Build Project and execute it, observe the output window. Building the software project takes some time. When the compilation is complete, the .dat files in the <project directory> are updated. --quartus_project_dir "C:/Users/TerryT/workspace/niosII_stratixII_2s60" Info: (BD_big_stack.elf) 89 KBytes program size (code + initialized data). Info: 31 KBytes free for stack + heap. Info: Creating BD_big_stack.objdump nios2-elf-objdump --disassemble --syms --all-header --source BD_big_stack.elf >BD_big_stack.objdump [BD_big_stack build complete] After creating and building the software project, follow these steps in Active-HDL in order to run the simulation. Running simulation in Active-HDL Please follow these steps once the simulation files generation in both SOPC and Eclipse are complete. Start Active-HDL, or if Active-HDL is already opened then close any opened workspace. Go to menu File>>Import>>Altera>>SOPC Simulation Script Browse to setup_sim.do file, select it and click on Open [setup_sim.do file can be found inside the project directory. This file is generated by SOPC builder] Figure 14: setup_sim.do file Altera SOPC Simulation Script importing wizard will create the workspace and will create and add the necessary do files to the workspace. Below is the typical output of the console after importing setup_sim.do file. The workspace is shown below as a result of importing the simulation script to Active-HDL. # ELBREAD: Elaboration time 2.5 [s]. # Reading "setup_sim.do" ... # Creating "setup_sim_altera.do" ... # Creating "comp_altera.do" ... # Creating "comp_mem_altera.do" ... # Creating "init_sim_altera.do" ... # Creating "wave_presets_altera.do" ... # Creating "list_presets_altera.do" ... # Creating "help_altera.do" ... # Creating "aliases_altera.do" ... # Creating "jtag_uart_0_log_altera.do" ... # Import process successfully finished, etc. Figure 15: Workspace after importing the setup_sim.do file Execute the comp_altera.do file to map and compile the required libraries. To execute the macro file, you can right click on the comp_altera.do file and click on execute. # Compile Architecture "europa" of Entity "onchip_memory2_0_s1_arbitrator" # Compile Entity "sysid_control_slave_arbitrator" # Compile Architecture "europa" of Entity "sysid_control_slave_arbitrator" # Compile Entity "timer_0_s1_arbitrator" # Compile Architecture "europa" of Entity "timer_0_s1_arbitrator" # Compile Entity "VME_HW_SOPC_BUILD_reset_clk_0_domain_synch_module" # Compile Architecture "europa" of Entity "VME_HW_SOPC_BUILD_reset_clk_0_domain_synch_module" # Compile Entity "VME_HW_SOPC_BUILD_reset_altpll_0_c0_out_domain_synch_module" # Compile Architecture "europa" of Entity "VME_HW_SOPC_BUILD_reset_altpll_0_c0_out_domain_synch_module" # Compile Entity "VME_HW_SOPC_BUILD" # Compile Architecture "europa" of Entity "VME_HW_SOPC_BUILD" # Compile Entity "test_bench" # Compile Architecture "europa" of Entity "test_bench" # Compile success 0 Errors 0 Warnings Analysis time : 0.8 [s] Execute the init_sim_altera.do file to initialize the simulation. Following messages will be printed on the console. # ELAB2: Elaboration final pass... # ELAB2: Create instances ... # ELAB2: Create instances complete. # SLP: Started # SLP: Elaboration phase ... # SLP: Elaboration phase ... skipped, nothing to simulate in SLP mode : 0.0 [s] # SLP: Finished : 0.0 [s] # ELAB2: Elaboration final pass complete - time: 1.2 [s]. # KERNEL: Kernel process initialization done. # Allocation: Simulator allocated 25170 kB (elbread=6156 elab2=16989 kernel=2025 sdf=0) # KERNEL: ASDB file was created in location C:\Users\TerryT\workspace\niosII_stratixII_2s60\VME_HW_SOPC_BUILD_sim\src\wave.asdb # 11:36 AM, Wednesday, February 02, 2011 # Simulation has been initialized # Selected Top-Level: test_bench (europa) Execute the wave_presets_altera.do file to add the signals to the waveform. You can execute the macro to add the signals or you can print w in the console and hit enter. Now run the simulation from the simulation menu or type run 1000 us in the console and hit enter. Console should display the following messages. # # Displays virtual signals # 6 signal(s) traced. run 1000 us # EXECUTION:: NOTE : Stratix II GX PLL is enabled # EXECUTION:: Time: 0 ps, Iteration: 2, Instance: /DUT/the_altpll_0/altpll_0_altpll_sd1_183/STRATIXII_ALTPLL/M1, Process: SCHEDULE. # EXECUTION:: NOTE : Stratix II GX PLL locked to incoming clock # EXECUTION:: Time: 110 ns, Iteration: 4, Instance: /DUT/the_altpll_0/altpll_0_altpll_sd1_183/STRATIXII_ALTPLL/M1, Process: SCHEDULE. # KERNEL: stopped at time: 1 ms The image below shows an example of a successful simulation run for 1msec. Figure 16: AHDL Simulation Run Previous article Next article
