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Installation of extra rulesets can be confirmed within the main tool and enabled via the policy editor. For license verification during setup, the license diagnostic tool provides ample information on the current license file and licensed modules. ALINT-PRO Demonstration Videos 1.0 Riviera-PRO™ Overview: Advanced Verification Platform Riviera-PRO™ addresses verification needs of engineers crafting tomorrow's cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. Riviera-PRO Demonstration Videos 1.1 Basics : Workspace A Workspace is comprised of individual designs containing resources such as source files and output files with simulation results. Learn how to create a new Workspace using the New Workspace Wizard, manage an existing Workspace, and manage the different components of the Workspace. Active-HDL Demonstration Videos 1.1 Basics: Perspectives and Favorites Perspectives are a configured interface which are comprised of different windows and views. When working at different stages of the design flow it can be useful to have different views open, which can be switched to with use of perspectives. Favorites are used to display select tools, macros, or user-defined commands in the interface and different views that are important to have accessible. Riviera-PRO Demonstration Videos 1.1 Basics: Running Design Entry and Linting ALINT-PRO's Flow Manager window allows managing the design analysis process in a convenient way. This video will show each step of the design flow, going through parse, elaboration, synthesis, constraints, and finally linting. At each step, more information about a project can be obtained. Additionally, each step includes various settings and configurable properties that allow for a highly customized linting process. ALINT-PRO Demonstration Videos 1.2 Basics: Design Flow Manager The Design Flow Manager (DFM) is designed to automate and simplify the design, synthesis, and implementation processes. The interface takes the form of design flowcharts which show the design path in graphical form. Learn how to enable the DFM, choose third party vendor tools for synthesis and implementation, and how to perform each stage of the synthesis and implementation processes. Active-HDL Demonstration Videos 1.2 Basics: HDL Editor and Templates The HDL Editor available in Riviera-PRO gives flexibility and provides advanced features to speed up the design process and make debugging easier. It provides shortcuts and tools in every stage of designing. Templates are available to use in the HDL Editor which provides basic constructs in various HDL and gives the option to create templates from code that's already written. Riviera-PRO Demonstration Videos 1.2 Basics: Importing and Running Other Designs Whether one chooses to develop their design in Active-HDL, Riviera-PRO, Quartus, or Vivado, ALINT-PRO can always be used to perform design rule checking via the tool's convert feature. Converting external project files into ALINT-PRO turns the source project files into the equivalent ALINT-PRO workspace and project structure. Once converted, the design is then accessible to all of the solution's linting and rule checking features. ALINT-PRO Demonstration Videos 1.3 Basics: Library Manager Learn how to create and manage user libraries, and how to utilize pre-compiled FPGA vendor libraries. Active-HDL Demonstration Videos 1.3 Basics: Outline for VHDL Users The Outline Viewer available in Riviera-PRO digests VHDL code and breaks it down into it's basic components. It will format and display different components of VHDL code and enable filtering and searching for signals and design objects, making large projects easy to navigate. Riviera-PRO Demonstration Videos 1.3 Basics: Violation Viewer and Reports ALINT-PRO's violation viewer provides a user friendly window for displaying and managing design rule violations. Coupled with automatic report generators, the tool helps not only to identify any violations within your design, but also document them so that they may be corrected and even prevented in later designs. Automatic report generators come in a number of formats, including CSV, PDF, HTML, as well as Quality Reports which provide metrics on how compliant a design is to a given rule set. ALINT-PRO Demonstration Videos 1.4 Basics: Block Diagram Editor The Block Diagram Editor (BDE) is Active-HDL's tool for graphical entry of VHDL, Verilog, and EDIF designs. This is especially useful to those with HDL designs that are largely structural since it is easier to enter descriptions graphically rather than typing hundreds of source code lines. Learn how to create a new block diagram by adding new ports, adding symbols, editing symbols (pin placement, pin names, etc.), connecting symbols with wires/bus, generate HDL code, and how to create a graphical testbench. Active-HDL Demonstration Videos 1.4 Basics: Workspaces, Projects, and Libraries Workflow in ALINT-PRO is organized through projects that are grouped into workspaces. A project will contain the set of properties and files, those being your HDL source code and design constraints, to form a single entity that makes up part of your design. Libraries are automatically generated at the local level and correspond to projects within the workspace. Additional libraries can be added through the tool's library export and attach features. ALINT-PRO Demonstration Videos 1.5 Basics: Encryption and Security Sharing Encryption and Secure Sharing is an important aspect for businesses that need to protect their IP against unauthorized utilization. Different levels of IP Encryption and Protection are required when modules are licensed, evaluated or transferred within departments. Riviera-PRO can deliver protected IP in two forms: encrypted source files or precompiled protected libraries. Riviera-PRO Demonstration Videos 1.5 Basics: FSM Editor Learn how to create a new Finite State Machine (FSM), define ports, add new states, transitions, actions, and conditions; add multiple state machines, generate HDL code, generate a testbench, and run a simulation to trace over the transitions to observe the functionality of the state machine. Active-HDL Demonstration Videos 1.5 Basics: Policy Editor The quality of linting results is largely dependent on one's policies and rules. Through the use of its policy editor, ALINT-PRO provides an effective means of managing and customizing those policies and rules to best fit the standards and practice of one's design team or company. ALINT-PRO Demonstration Videos 1.6 Basics: HDL Editor The HDL Editor is a text editor for editing HDL source code. It contains features such as keyword coloring (VHDL, Verilog/SystemVerilog, C/C++, SystemC, OVA, and PSL), recording/playing actions, bookmarks, hyperlinks to files, creating structure groups, breakpoints, autoformat/smart indentation, etc. Learn how to create a new HDL file with the New Design Wizard and how to utilize the HDE features within that created source file. Active-HDL Demonstration Videos 1.6 Basics: Project Tasks Management Using Tasks in your Riviera-PRO Project allows you to track and prioritize assignments inside of a project. Tasks can be assigned to different areas of your project and will help outline the order and how quickly things should be completed. Riviera-PRO Demonstration Videos 1.6 Basics: Waivers Waivers provide an excellent service in managing violations during the linting process by ignoring those violations or sources of violations that might be too pessimistic for or not applicable to one's design. ALINT-PRO's interface provides an easy process for adding and removing these waivers no matter the source. Additionally, the tool's waiver editor provides a single location where one can manage and edit an entire project's waiver list, and even export this list for future projects. ALINT-PRO Demonstration Videos 1.7 Basics: Compilation and Simulation Learn how to specify design settings for compilation (setting up debugging windows, selecting maximum optimization, etc.), how to initialize and run simulations, how to view the simulation results, and how to perform compilation and simulation with scripts. Active-HDL Demonstration Videos ... 287 results (page 1/15)