The Science of Verification

Science is a product of endless counts of trial and error. Without an error, how can we tell that something is right? This is the main reason why we perform verification.

Verification has never been more complex. Engineers would like cover as much useful data as possible when reviewing a verification plan. It is an irony, but finding errors within a design can be a positive, as the design is “more correct” after fixing these errors. However, it is not quite easy to design a testbench that is directed to find errors. In some cases, these errors are caused by corner cases that were not tested during prior simulation. A good source of these data is the coverage report.

Active-HDL™, Aldec’s FPGA design creation and simulation solution, provides the following coverage reports:

• Statement Coverage - details which part of the design was executed and which was not, which helps to locate dead code
• Branch Coverage - identifies branch statements (f and case) that are (are not) executed
• Path Coverage - analyzes whether all possible sequences of program execution were verified
• Expression Coverage - evaluates logical expressions and determines when all of the expression cases are exercised
• Assertion Coverage - looks at all the assertions (PSL, SVA and OVA) and defines which properties have been covered
• Toggle Coverage - measures design activity in terms of changes in signal logic values

The results of these reports can help us steer our test bench to cover cases that we would not have covered before. These reports can boost the verification plan and give it more confidence.

In this video we will discuss how to configure your design to collect coverage data: