A Comprehensive RTL Verification Solution for VHDL

ALINT-PRO™ Design Rule Checking Solution

Pavel Leshtaiev, Product Manager Software Division
Like(2)  Comments  (0)

On Thursday, November 19, I’ll be hosting a webinar to demonstrate Aldec’s RTL Verification Solution for VHDL, ALINT-PRO™ Design Rule Checking Solution.


ALINT-PRO is Aldec’s design verification solution for RTL code focused on general issues analysis including RTL and post-synthesis simulation mismatches, design coding for optimal synthesis, avoiding problems on further design stages, coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design time dramatically.


It is important to note that ALINT-PRO 2015.10 contains only VHDL and Netlist rule libraries. (Verilog and SystemVerilog support will be included in future releases.)


With this release, ALINT-PRO-CDC™ for CDC Verification also became available as a language-independent rule-plugin to ALINT-PRO.


ALINT-PRO also leverages the same set of license features as ALINT™ (classic version which remains available as a stand-alone product). Existing ALINT customers with valid maintenance are able to run ALINT-PRO with current license (including rule plug-ins support).


Recorded Webinar:

Fast Track to ALINT-PRO: Design Entry and Linting

This “Fast Track” series webinar is designed to help engineers get up to speed quickly with ALINT-PRO. Learn how to prepare designs for analysis in ALINT-PRO and obtain linting results. In this webinar, we will also cover workspace and project setup, library management, linting configuration, and violation analysis.


ALINT-PRO 2015.10 Highlights Include:


Industry Proven Guidelines In addition to Aldec-developed rules, ALINT-PRO supports design checks based on STARC (Semiconductor Technology Academic Research Center) design guidelines, which utilizes best practices in design developing used by semiconductor companies all over the world. For safety critical designs, Aldec delivers rule libraries based on DO-254 guidelines focused on critical issues analysis that impact design stability.


Design Constraints Support ALINT-PRO recognizes industry proven SDC™ (Synopsys Design Constraints) commands for design configuration making it possible to utilize real design configurations without a need of synchronizing with custom preference format.


Enhanced User Experience Based on the feedback from ALINT customers, Aldec presents ALINT-PRO as a fully reworked and written from scratch solution. It features schematic viewer, automatic conversion of third party workspaces into native format, integration of all artifacts required for linting in a single workspace, and a well-developed set of console commands for efficient integration in a continuous integration flow.


CDC Verification ALINT-PRO features ALDEC_CDC plug-in enabling full power of CDC and RTL analysis in the single tool and extending verification with dynamic checks via integration with simulators (Riviera-PRO™, Active-HDL™, ModelSim®)


Download a free evaluation at www.aldec.com/Downloads.


For questions or to purchase, please contact sales@aldec.com or your local distributor.


For more details see, ALINT-PRO 2015.10 Overview Presentation and ALINT-PRO 2015.10 Release Notes.

Pavel is a Product Manager at Aldec for DRC and CDC solutions. He received his MS in Special-Purpose Computer Systems from the Chernihiv State University of Technology, Ukraine. Pavel has been directly with ALINT™ and ALINT-PRO-CDC™ since 2009, with experience in roles such as SQA Engineer, SQA Team Leader, Applications Engineer, Project Manager and Product Manager. He has deep practical experience in design verification techniques and best practices, particularly in the field of FPGA design.


Ask Us a Question
Ask Us a Question
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.