Increased Debug Capability with Hardware Emulation

Bill Jason P. Tomas, Product Engineer, Hardware Division
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Hardware emulators enable a rich environment for debugging complex SoC esigns by providing advantages from both software and hardware. Typically, in software simulation designers can set breakpoints, observe waveforms, and trace signals as they progress through a test bench, but are constrained by the speed of the simulator. In hardware, designers can take advantage of the higher clock frequency, real-world stimulus, but are bogged down by the task oftracing bugs in the code without sufficient information of what is occurring during system operation. Hardware emulators that utilize multiple modes of verification (acceleration, emulation, and prototyping) can provide designers the speed and debug tools required for today's SoC designs at all stages of development.


During SoC development, designers require different debugging capabilities at each level of the design. Hardware designers working primarily with RTL code can leverage simulation acceleration as it concentrates on the bit-level. For higher levels of the design, RTL modules are connected to the rest of the SoC using transaction level modeling or virtual platform. System architects or verification engineers would see greater benefit here if they were to employ a higher abstraction layer based on transactions.


In the design phase, hardware engineers working within an RTL environment handle numerous HDL files, each with multiple layers of hierarchy. They also integrate multiple IP cores, processors, memory modules, and peripherals into the SoC. Designers on this level have certain debugging requirements to test the integration of all these modules within a hardware platform. They must be able to trace signals both in the simulator as well as in hardware to verify that the system in functioning correctly.


HES-DVM™ from Aldec provides multiple debugging capabilities which allow designers to work in a bit-level environment, accelerating the time required to find and solve issues:

  • Static Probes allow users to specify design internal signals for debugging in the HDL design. This specification will be available in the simulator and can be observed directly in a waveform viewer;
  • Black Box Signals exclude design structures from hardware in order to simulate them in an HDL simulator. This is helpful when non-synthesizable constructs are buried deep in the design hierarchy;
  • Mirror Box Signals are not excluded from hardware, but are mirrored in HDL simulation. This is particularly helpful where hardware models behave differently from HDL simulation.

Img1 w Fig.1-01

In the verification phase, system architects and verification teams continue to require a higher level overview of the system to validate that all portions of the SoC work together correctly. Once again, this can be accomplished using transaction level modeling or virtual platforms. For this stage of development software designers will continue to have their own set of debugging requirements and may require accessing memory to verify correct values, checking values of process registers, or setting up signal triggers for logic analyzers. Verification teams may also need to use test sequences written in other languages other than Verilog/VHDL, which may be C, C++, SystemC, or SystemVerilog.


HES-DVM™ addresses these verification requirements by leveraging:

  • Dynamic debugging to deliver configurable access to any register in the system design;
  • Hardware-based Visibility Debug (Figure 2) to analyze design RTL sources to identify the minimum number of debugging probes that must be present in the emulation hardware to guarantee 100% debug visibility;
  • Memory Debugging to allow viewing contents of all memory mapped instances in HES-DVM. This enables changing of contents of a single memory cell or an entire block and saving and loading memory contents to and from a source file; and
  • Advanced Logic Analyzer, a debugging tool capable of 16 separate trigger ports, each having a maximum width of 256 bits.

Img2 w Fig.2-01-01

HES-DVM provides numerous debugging capabilities for different modes of verification, allowing SoC designers to take advantage of the rich debugging environment of RTL simulation with the speed of hardware implementation. As ASIC’s and SoC's continue to grow larger and more complex, the HES ecosystem continues to meet the needs of design and verification teams. Learn more.

Bill is responsible for Aldec Hardware Emulation and SoC / ASIC Prototyping. He received his B.S. in Computer Engineering from Auburn University in Alabama in 2011, and currently undertaking his M.S in Electrical Engineering with a focus on hardware emulation methodology and Built-In-Self-Test for high capacity FPGAs. He is also currently a graduate research assistant for the University of Nevada Systems and Integration laboratory studying Network-on-Chip BIST strategies. 

  • Products:
  • HW-Assisted Verification


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