Verilog-AMS & Multi-Level Simulation

Aldec and Tanner EDA Bridge Digital and Analog Design Flows

Mariusz Grabowski, FPGA Design and Verification Engineer
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It occurred to me that it has been a few months since we shared an update on HiPer Simulation A/MS. Following DAC 2013 and Daniel Payne’s posts at SemiWiki (post 1, post 2), we at Aldec and Tanner EDA have received many inquiries from the field, conducted a number of evaluations, and deployed our analog/mixed-signal (AMS) design flow with our first mutual customers. In this article, I’ll share more the mixed-signal simulation methodology and highlight some of Verilog-AMS use cases that we have seen in the field.


Digital & Analog HDLs

The Verilog and VHDL languages were designed to handle discrete signals, where the number of possible signal values is limited (e.g. 1, 0, X, Z). Whereas Verilog-A was designed to handle continuous-time (analog) signals, that can take any value from a continuous range at any point.

Verilog-AMS and VHDL-AMS are the two HDLs currently available for describing mixed-signal hardware. As the “AMS” part suggests, they enable modeling of systems that process both digital and continuous-time. As such, Verilog-AMS combines two languages (Verilog and Verilog-A) and also provides an extension to allow description of mixed-signal components:

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An example of a mixed-signal system is presented in the following diagram:

ams simulation, verilog-ams, verilog ams, verilog ams simulator

Another way to think about Verilog-AMS is as an extension of SPICE, raising the level of abstraction available to analog and mixed-signal designers:

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Mixed-Signal Design Approach

Digital and analog designers are indeed still living in separate worlds, using different methodologies and tools. Even though Verilog-AMS is available, most of the mixed-signal designs use the bottom-up approach:

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Why would they do that while Verilog-AMS is available?


Bottom-up approach:

Opponents of the bottom-up design approach start designing the individual blocks, implement them at a transistor level, verify them individually, and then combine the blocks to form the system – entirely represented at the transistor level.

One of the biggest arguments for the bottom-up design is that analog designers don’t have access to automated tools such as the place & route technology that made the top-down approach a de-facto standard for digital. Another is that custom design may be the only way to achieve performance; a highly custom circuit is typically required to fit the requirements of a particular application.

Perhaps the biggest challenge of the bottom-up design approach is that system level is reached late at the design cycle, when it’s too late for any major architectural changes even if they could improve performance dramatically.


Top-down approach:

Opponents of the top-down approach are trying to tackle the key challenge of the bottom-up approach, putting themselves in charge of the architectural exploration. In terms of the top-down paradigm, the design starts with a block-level definition of the system and simulation in a system simulator such as MathWorks Simulink or Agilent SystemVue; the individual blocks are then designed at the transistor level based on the requirements derived from the system-level simulation; and finally the entire chip is assembled from blocks and verified.

While top-down design approach has a number of obvious benefits at the architectural level, it still comes down to designing analog parts of the mixed-signal system manually for the sake of performance and creativity. However we see more and more customers employing the top-down approach due to a benefit which might be easy to overlook – the ability to incorporate mixed-level simulation easily.


Mixed-Level Simulation

Neither the bottom-up nor top-down approach addresses the simulation-based verification challenge at the system level (it takes too much time to simulate a large system defined at the transistor level). To overcome this challenge, the mixed-level simulation is use.

The idea is relatively simple and involves replacing a top-level block with its transistor-level implementation, and then co-simulating the two levels of abstraction to verify the block in the context of the system (such as a testbench).

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The mixed-level simulation is not limited to co-simulation at just two levels of abstraction. The system simulators (Simulink & SystemVue) can auto-generate Verilog-HDL to be shared with the digital and mixed-signal design teams for further replacement with the Verilog-AMS models and/or SPICE netlists. So, you might end up co-simulating top-level (system) description with behavioral Verilog-AMS and with transistor-level (SPICE) model at the same time.


Verilog-AMS Simulators

Since in a mixed-signal system, signals from both the discrete (digital) and the continuous domain (analog) are used, simulator vendors need to include two kernels, event-driven (logic simulator) and continuous (circuit simulator). The following block level diagram presents Aldec/Tanner EDA integration in terms of HiPer Simulation A/MS tool suite:

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Some vendors in this market claim to have a “single-kernel” AMS simulator, but chances are that they still have good-old co-simulation between the two kernels under the hood. This is exactly how HiPer’s mixed-signal environment works, enabling users to deal with the standard Verilog-AMS input language, and then automatically separating SPICE and Verilog, inserting interface components, running simulation, and displaying results.


Let’s Run a Sample Design

Tanner EDA hosts both the tools, and users can download the package from Tanner’s website at

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The package includes Tanner Edition (TE) of Riviera-PRO, a limited yet still capable mixed-language simulator. The installation process is straightforward with the only possible caveat is that users who elected for 64-bit version of Tanner Tools must go with 64-bit version of Aldec Riviera-PRO as well. Once the tools are installed and licenses are set up, the user must set the TANNER_ALDEC_DIR environment variable pointing to Riviera-PRO installation and the HiPer Simulation A/MS platform is ready to go.

Loading the ADC8 example in Tanner’s S-Edit provides a quick way to test-drive the mixed-signal simulation. This is how the ADC8 schematics look like:

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Selecting the green “Run Simulation” arrow will automatically write out the netlist, including SPICE and Verilog components, and invoke T-Spice.

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T-Spice splits the design into SPICE, Verilog-D and Verilog-A (Verilog-AMS modules are split), and invokes Aldec’s Riviera-PRO TE:

 ams simulation, verilog-ams, verilog ams, verilog ams simulator

The simulation runs until completion, and results are shown in W-Edit:

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Creating and verifying A/MS integrated circuits is a challenge. SPICE-based simulation provides the accuracy needed for the analog design, but is too slow to handle the system level verification. Event-driven digital simulation provides the necessary speed to simulate the digital portions, but fails when dealing with the analog parts. Verilog-AMS is the language that brings the digital and analog worlds together, enabling efficient top-down design approach but introducing co-simulation challenges.

The integrated Aldec/Tanner solution helps to eliminate co-simulation complexities by automatically recognizing the analog and digital portions of a design and enabling designers to easily verify interfaces between analog and digital blocks. HiPer Simulation A/MS provides accurate, high-performance co-simulation that allows designers to verify the most complex A/MS designs with ease and confidence, and within budget.

A free no-obligation 30-day evaluation license is available at

Mariusz Grabowski is an FPGA Design and Verification Engineer at Aldec. He works in the field of verification for DO-254 compliance as well as developing digital processing systems. He is proficient in digital design and verification, using hardware description languages such as Verilog/SystemVerilog and VHDL, and the use of verification methodologies such as UVM.

Mariusz is a student at the AGH University of Science and Technology in Krakow, Poland. He also gains practical experience in the AVADER Scientific Group (where he designs novel vision systems on FPGAs) and in the Integra Scientific Group (where he acquires knowledge about microprocessor systems and electronics).


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