Aldec Design and Verification Blog Trending Articles Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM The Convergence of Emulation and Prototyping All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Effective Communication is Key in Relationships… and ESL Design! Aldec & Agilent EEsof improve digital/ESL relationship with COMRATE™ engine COMRATE™, the co-simulation solution developed by Aldec and Agilent is a lot like “couples-therapy” that can help get your digital blocks talking to the rest of your model-based design.... Tags:Co-simulation,Debugging,Mixed-signal,Verification Like(3) Comments (0) Read more Driving Innovation in Image Sensors and High Speed Analog/Mixed-Signal Design Guest Blog with John Zuk from Tanner EDA Aldec Product Manager, Dmitry Melnik, recently shared a blog update on Verilog-AMS & Multi-Level Simulation. Within the many inquiries he mentions, we noted a consistent theme... Tags:Analog,Digital,Mixed-signal,Simulation Like(2) Comments (0) Read more Verilog-AMS & Multi-Level Simulation Aldec and Tanner EDA Bridge Digital and Analog Design Flows It occurred to me that it has been a few months since we shared an update on HiPer Simulation A/MS. Following DAC 2013 and Daniel Payne’s posts at SemiWiki (post 1, post 2),... Tags:Analog,Digital,Mixed-signal,Simulation Like(1) Comments (0) Read more Back from DAC Functional Verification Insights from Austin I just returned back to the office from the 50th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight.... Tags:Functional Verification,Mixed-signal,SoC,SystemVerilog,Training,Verification,Verilog Like(3) Comments (0) Read more
