Aldec Design and Verification Blog Trending Articles Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM The Convergence of Emulation and Prototyping All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications What inspired you to become an engineer? National Engineering Week is February 22-28 This week, February 22-28, we celebrate National Engineers Week in the US to recognize the contributions to society that engineers make. During this time, there is added emphasis in schools on the importance of learning... Tags:Aceleration,Analog,ARM,Aviation,Co-simulation,FPGA,Functional Verification Like(1) Comments (3) Read more Driving Innovation in Image Sensors and High Speed Analog/Mixed-Signal Design Guest Blog with John Zuk from Tanner EDA Aldec Product Manager, Dmitry Melnik, recently shared a blog update on Verilog-AMS & Multi-Level Simulation. Within the many inquiries he mentions, we noted a consistent theme... Tags:Analog,Digital,Mixed-signal,Simulation Like(2) Comments (0) Read more Verilog-AMS & Multi-Level Simulation Aldec and Tanner EDA Bridge Digital and Analog Design Flows It occurred to me that it has been a few months since we shared an update on HiPer Simulation A/MS. Following DAC 2013 and Daniel Payne’s posts at SemiWiki (post 1, post 2),... Tags:Analog,Digital,Mixed-signal,Simulation Like(1) Comments (0) Read more
