DO-254/CTS™ solves Elbit’s major challenges

Helps them pass EASA Verification Audit

Louie de Luna, Aldec DO-254 Program Manager
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Aldec has been working closely with Elbit Systems in Israel on an important DO-254 project for some time now. Using Aldec’s specialized solution DO-254/CTS™ as their primary FPGA physical testing platform, Elbit recently passed a critical EASA verification audit for DO-254/ED-80 DAL A FPGAs.

As a DO-254 evangelist, I have long recognized the value and benefits of Aldec’s solution to the avionics industry, so it was particularly rewarding to hear these words from Moshe Porian, Logic Design Verification Group Leader at Elbit Systems Aerospace Division, “Aldec helped us solve several of our verification challenges. This is the first time in Elbit’s history that we have been able to bring more than 5 FPGA devices to the audit.”  

DO-254/CTS solved Elbit’s major challenges, enabling them to test in hardware 100% of FPGA pin-level requirements. As opposed to developing software test vectors, Elbit used their simulation testbench as test vectors for FPGA at-speed testing which cut their development costs. For further details, see the full Press Release: Elbit Systems deploys Aldec DO-254/CTS and Passes EASA Verification Audit for Level A System.


DO-254 Verification via Simulation or Test?

While the DO-254 guidance is vague as to how much verification should be achieved via simulation or test in the target board, it is quite clear that requirements describing FPGA pin level behavior must be verified by test in physical hardware in order to satisfy the objectives of DO-254. Verification coverage by test during target board testing is difficult and in most cases not feasible. Frequently as a result, applicants are left with the only option to verify them only by simulation.

But simulation is insufficient. Simulation only uses models which are not a real representation of the device. Aldec’s DO-254/CTS augments board level testing to increase functional verification coverage by test. DO-254/CTS provides 100% verification coverage by test with 100% FPGA input control necessary to implement requirements-based and robustness test cases and leverages the same test cases and test stimulus implemented in simulation for device testing. This offers a more efficient verification approach, along with the ability to cut the verification cycle.


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Louie de Luna is responsible for FPGA level in-target testing technology and requirements lifecycle management for DO-254 and other safety-critical industry standards.  He received his B.S. in Computer Engineering from University of Nevada in 2001.  His practical engineering experience includes areas in Acceleration, Emulation, Co-Verification and Prototyping, and he has held a wide range of engineering positions that include FPGA Design Engineer, Applications Engineer, Product Manager and Project Manager.

  • Products:
  • DO-254/CTS
  • FPGA Test System


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