Setting up Source Code Analysis for SystemVerilog Compilation

Introduction

The HDL Editor allows instant verification of VHDL or Verilog/SystemVerilog source code prior to starting a regular compilation process. Source code analysis running in the background while developing HDL code, is a preliminary source of information allowing you to find out whether newly created source code is error-free, or if it still requires corrections.

How to use Code Analysis

The analysis is performed automatically whenever you start typing in new lines of source code, or after you paste a block of a code, e.g. copied to the clipboard or inserted by using the code Autocomplete feature. When a portion of an edited block of source code is complete and its syntax is correct, a new item representing this block is displayed in the Outline window. Otherwise, if an issue with syntax or code integrity is detected in an HDL file, an error marker is displayed in the HDL Editor window. Erroneous lines or incomplete portions of code are pointed by the red marker(s) on the left margin of the HDL Editor window as shown in Figure 1.

Figure 1.

If you hover the mouse-pointer over the error marker, a tooltip is displayed. It shows an ID of an error and a short error message explaining potential discrepancies in source code, and what should be checked or modified in order to correct an error.

Use in SystemVerilog Designs

In SystemVerilog designs, source code analysis may “mistakenly” red mark some lines because the functions or classes used in the file are defined in an `include file located outside the current working directory. For the designs that include external files, the working environment has to be configured properly. This is typical for UVM designs that use a lot of includes.

Workspace based approach

If you have a workspace/design open, to remove the un-wanted red markers in the HDL editor you can follow one of the options below:

Option 1: Add the include files as SystemVerilog entries in the design Properties.

Right click on the design name and then select Properties. In the Properties dialog box, Go to Compilation | SystemVerilog | Entries. Here, add the directories that contain the include files as shown in Figure 2.

Figure 2.

Go to Tools menu | Preferences | Tools | HDL Editor | {VHDL | SystemVerilog}) Here you can check the Only for files in workspace option as shown in Figure 3.

Figure 3.

Figure 4.

Option 2: Disable source code analysis completely.

If you want to completely disable source code analysis, Go to Tools | Preferences | Tools | HDL Editor | {VHDL | SystemVerilog}) Here, uncheck the Enable automatic code analysis as shown in Figure 4.

File Browser based approach

If you do not have a design and you are running the tool using scripts, then you can follow the below options to remove the “faulty” red markers.

Option 1: Add the include files as system verilog entries of global preferences dialog box.

Go to Tools | Preferences | Compilation | SystemVerilog | Entries. Here, add the directories that contain the include files as shown in Figure 5.

Figure 5.

Option 2: Disable Source Code Analysis completely.

If you want to completely disable source code analysis, Go to Tools | Preferences | Tools | HDL Editor | {VHDL | SystemVerilog}) Here, uncheck the Enable automatic code analysis as shown in Figure 4.