Getting Started with Active-HDL in Diamond

Introduction

This tutorial provides instructions for using Active-HDL in Diamond. Active-HDL is an integrated environment designed for development and verification of VHDL, Verilog, System Verilog, EDIF, and System C based designs. In this tutorial we use a sample VHDL design provided by Lattice Diamond to perform design entry and simulation.

Getting Started

You will first need to install Lattice Diamond Design Software and the latest version of Active-HDL to be able to successfully complete this tutorial. The free downloads are available here: Active-HDL and Lattice Diamond. You will then need to request a license to run the Diamond Design Software and request an Aldec license.

Creating Workspace and Design

At the start page of the Lattice Diamond, you will be able to create a new Project.

Click on New under Project or click File | New | Project. The New Project Wizard starts.

Figure 1: Create New Project
Click Next.
Provide the Project Name, Project Location, Implementation Name, and Implementation Location.

Figure 2: Create a New Project Wizard
Click Next.

Figure 3: Add Source Files
If you have any source files select Add Source. (You can select to Copy source to implementation directory).
Click Next.
Select Target Device.

Figure 4: Specify Target Device
Click Next.
Select Synthesis Tool by clicking Lattice LSE for this tutorial.

Figure 5: Select Synthesis tool
Click Next.

Figure 6: Project Information
Project Information with specification that were previously selected will be displayed. If everything is correct, select Finish.

Creating/Adding Files to Design

A Project Summary that includes Reports will be displayed. The project's file list, process, hierarchy, and the console will also be displayed.

Figure 7: Project Summary
To create a new file or an existing file, right click Input Files and click Add -> New File.
You can also use File | New menu to add new files or open existing files and save it to the design directory.

Figure 8: Add New Files

Creating HDL Source Code

Choose the desired source type, provide a name, and click New.

Figure 9: Create Source Files
After selecting the source file type, a new editor window will open and will be ready for design entry.

Specify Path to Design

Add the path for Aldec Simulator by going to Tools | Options and selecting Environment -> Directories under Simulation:, provide the path for Active-HDL.

Figure 10: Aldec Simulator Path
Click Apply.
Click Ok.

Simulation

To start Simulation Wizard, go to Tools | Simulation Wizard

Figure 11: Simulation Wizard
Click Next.

Figure 12: Simulator Project Name
Provide the Project Name and the project location. Then select Active-HDL for Simulator.
Click Next.

Figure 13: Process Stage
Choose RTL and then click Next.
Add and Reorder Source Files by using the arrows to organize files, you can also add or delete source files.

Figure 14: Add and Reorder Source Files
You may select Copy Source to Simulation Directory and/or Automatically set simulation compilation file order.
Click Next.

Figure 15: Parsing HDL Files
Parsing of HDL files occurs and once finished, click Next.
A summary is displayed, if any changes need to be made click Back.
- Check Run Simulator
- Check Add top-level signals to waveform display
- Check Run Simulation
- Click Finish.
If no changes are needed, click Finish

Figure 16: Simulation Summary

Active-HDL

Active-HDL will open up automatically. Waveform Viewer, Design Browser, and Console will be displayed.

Figure 17: Active-HDL

Waveform Viewer

By default, the Accelerated Waveform Viewer is enabled and an *.asdb simulation database is created upon initialization of simulation. The Accelerated Waveform Viewer should be the preferred choice for designers working with large amounts of simulation data. It is optimized for large designs and long simulation runs.

Upon Active-HDL opening up, simulation has already started. However, you can run simulation for an unspecified amount of time by choosing Run from the Simulation menu.
To advance a simulation by a specific time step, set the desired time step in the Simulation Step box located in the main toolbar. Choose Run for from the Simulation menu or choose Run Until from the Simulation menu. Specify the desired time until a simulation should run and then click OK.

Figure 17: Run Simulation

PAUSE/End Simulation

To pause the simulation at the current simulation time, choose the Pause option from the Simulation menu.
To finish the simulation session, choose End Simulation from the Simulation menu.
You can restart the simulation, select Restart Simulation from the Simulation menu.

Saving the waveform file for off-liine viewing

You must stop the simulation before saving by clicking End Simulation from the Simulation menu.

When the simulation is finished or has run for the given time, you can save the waveform using File | Save menu.
You can open a saved .awc file for off-line viewing.

HELP

Within the tool

Go to menu Help | Product Help to learn more about Active-HDL.

Help on web

Go to Aldec Support to access the online database and other technical documents about Active-HDL.