In the HES-DVM generated SystemC wrapper, there are some interface signals which are not in the list of I/O signals of DUT, what is the purpose of these signals?

sc_core::sc_signal<bool> p0; sc_core::sc_signal<bool> p1; . . sc_core::sc_signal<bool> p63;


Signals p0, p1,...p63 come from HES mapping file. This is how we reference each bit of DUT interface in hardware. Concatenation to real signals is done in SystemC or VHDL/Verilog wrapper.

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