1.9 Basics: Testbench Creation Testbench creation is a tedious but necessary process for verifying your designs. Once a design is ready for testing you are able to automatically generate testbenches and VHDL declarations within Riviera-PRO from Verilog, VHDL, or SystemVerilog source files. Use Riviera-PRO to speed up you testbench creation for all of your projects.
