Enhancing CDC Verification in Vivado with ALINT-PRO (US) Apr 10 (Webinar, Online) Enhancing CDC Verification in Vivado with ALINT-PRO (EU) Apr 10 (Webinar, Online) VHDL/SystemVerilog RTL verification environment by cocotb Apr 17 (Webinar, Tokyo, Japan ) Improved design reliability by lint tool Apr 23 (Webinar, Tokyo, Japan ) FPGA Verification with VHDL and UVVM: New Features and Best Practices (EU) May 08 (Webinar, Online) View all events
Maximizing Design Reliability with Advanced Linting: Uncover Hidden RTL Issues Early Simplifying DO-254 Compliance for FPGA Designs – A Practical Approach Mastering SoC Design and Verification for DO-254 Compliance – Balancing Complexity and Safety (Hosted by ConsuNova) Navigating COTS-IP in DO-254 – Strategies for Safe and Efficient FPGA Design (Hosted by ConsuNova) Static and Dynamic CDC Verification of AXI4 Stream-based IPs View all webinars
What’s involved in simulation of a complex SoC FPGA like Versal ACAP? February 08 Aldec @ DAC 2023: Presenting Design Verification Tools and Solutions for FPGAs and SoCs June 26 Riviera-PRO Supports System Simulation of AMD® Versal™ ACAP Designs June 14 The avionics industry’s growing need for TLM May 18 Aldec and Thales to Co-Present at Certification Together International Conference 2023 May 01 View all news