Back from DAC

Functional Verification Insights from Austin

Mariusz Grabowski, FPGA Design and Verification Engineer
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I just returned  back to the office from the 50th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight.



Conference itself

One of the reasons I like DAC is that it has always been the main industry event, attracting people from all over the world, and provides participants with the opportunity to meet most of their key customers, ecosystem partners, and competitors in a single location. From an exhibitor’s perspective, DAC is mainly about engaging with attendees on the floor, learning about their current and anticipated challenges, and educating them on how they can innovate and succeed using our product offerings.


Presentations and discussions

Back from DACAs usual, Aldec and our ecosystem partners had a productive time at DAC this year, connecting with attendees for a variety of live presentations and demos, showing them the latest advantages in system development, functional verification, mixed-signal simulation, high-level synthesis, and HW/SW co-verification.


We will be hosting a series of upcoming webinars to deliver these sessions to those of you who couldn’t attend. More details can be found here.


Functional Verification trends

Since Aldec’s core competency is functional verification, I was keeping an eye on this particular domain… and just by looking at the exhibiting companies, I can tell that both interest and presence in the functional verification space keep growing from year to year. This is no surprise to any major EDA vendor, as our customers have been designing complex multimillion SoCs for quite a while now.


  • We all know that verification is becoming more and more challenging as design complexity keeps growing. No one is surprised to see customer designs that target sub-28nm process technology, have billions of transistors, multiple ARM Cortex processors, a number of switchable power domains, and hundreds of IPs talking to each other via high-speed AXI interconnects.


  • Verifying a large-scale SoC is a process that requires careful planning and execution. SoC verification teams put a lot of pressure on EDA vendors and expect us to have their backs in achieving verification closure. While simulation remains one of the key verification methods, the tool efficiency has had a huge impact on project schedules.  For this reason, there is an on-going collaboration between Aldec customers and R&D to fine-tune Riviera-PRO™ based on the current cutting edge projects. We are constantly improving the compilation times for RTL code and gate-level netlist (with and with no SDF), simulation runtimes, and memory footprints.


  • Customers manage their requirements and test plans in dedicated tools such as Aldec's new Spec-TRACER™, and test new features with several constrained random sequences instead of thousands of directed tests, improving productivity by orders of magnitude. Functional coverage has always been going together with constrained-random stimuli, but today we are dealing with hundreds of functional coverage points, cross-coverage, and merging results from many test runs. Fortunately, standards such as Accellera’s UCIS help all vendors to address this challenge in a consistent and effective way.


  • SystemVerilog-based UVM and reusable Verification IPs (VIPs) is becoming an industry standard. Some teams reported that they were able to reduce design time by 2—3X based on deployment of UVM-compliant environments. UVM itself presents a challenge for EDA vendors – industry-wide adoption of this OOP-flavored framework requires us to shift some of the traditional paradigms and expand hardware engineer’s toolbox with new debugging tools, which used to be specific for software programming domain.


  • When it comes to an SoC design there are usually both software and hardware design teams, each using several techniques to be able to work in parallel and shorten time-to-market. These techniques include virtual prototyping, FPGA-based prototyping, and in-circuit emulation. Based on how customers use our HES-DVM™, we see that virtual prototyping is typically used for early software development and driver software verification; whereas primary application for emulation is verification of a sub-system or entire SoC in its system environment (connections to peripherals and software running in processors).


Well, I could go on and on… as I haven't even mentioned the challenges associated with low power design, multiple clock domains (CDC), high-level synthesis (HLS), and formal verification. Aldec has been around for 30 years, and we have seen designs evolve from few thousand gates to millions of gates… and today’s multimillion gate SoC will eventually become building blocks (or IPs) for the future SoC designs. These are certainly exciting times for the EDA industry!

Mariusz Grabowski is an FPGA Design and Verification Engineer at Aldec. He works in the field of verification for DO-254 compliance as well as developing digital processing systems. He is proficient in digital design and verification, using hardware description languages such as Verilog/SystemVerilog and VHDL, and the use of verification methodologies such as UVM.

Mariusz is a student at the AGH University of Science and Technology in Krakow, Poland. He also gains practical experience in the AVADER Scientific Group (where he designs novel vision systems on FPGAs) and in the Integra Scientific Group (where he acquires knowledge about microprocessor systems and electronics).


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