Aldec Design and Verification Blog Trending Articles Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM The Convergence of Emulation and Prototyping All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Navigating VUnit: A Practical Guide to Modifying Testing Approaches In the two previous blogs, we introduced you to the world of VUnit, guided you through creating a project from scratch, and demonstrated how to run multi-threaded unit testing of multiple independent tests.... Tags:Aceleration,Functional Verification,HDL,Riviera-PRO,Simulation,Verification,VHDL Like(0) Comments (0) Read more Speeding Up Simulation with VUnit for Parallel Testing Effective simulation is essential in hardware development, as time and accuracy are critical factors that can determine the success or failure of a project.... Tags:Aceleration,Functional Verification,HDL,Riviera-PRO,SystemVerilog,VHDL Like(0) Comments (3) Read more Introduction to VUnit In the realms of HDL code verification, where precision and efficiency are crucial, a great hero has emerged; VUnit. This open-source framework for VHDL/SystemVerilog has been making waves in the industry,... Tags:Aceleration,Functional Verification,HDL,Riviera-PRO,VHDL Like(0) Comments (0) Read more FPGA Design Verification in a Nutshell FPGA Design Verification (Planning) in a Nutshell Before wading into this topic, I’d like to state why I felt compelled to write about FPGA design verification. I recently presented a very well attended three-part webinar series, during which many attendees asked for book recommendations.... Tags:ASIC,Coverage,Design,Functional Verification,Debugging,Documentation,Digital,SoC,Verification,Verilog,VHDL Like(0) Comments (0) Read more Versal ACAP Simulation Challenges The electronics industry is all about optimization, and always has been. For example, you might think of system on chip (SoC) as a relatively recent term, coined this century. However, many regard the silicon that appeared in digital watches in the 1970s as constituting a system on a chip, ... Tags:Embedded,FPGA,Riviera-PRO,FPGA Simulation,Functional Verification,safety-critical,SystemC,SystemVerilog,VHDL,UVM Like(0) Comments (0) Read more What inspired you to become an engineer? National Engineering Week is February 22-28 This week, February 22-28, we celebrate National Engineers Week in the US to recognize the contributions to society that engineers make. During this time, there is added emphasis in schools on the importance of learning... Tags:Aceleration,Analog,ARM,Aviation,Co-simulation,FPGA,Functional Verification Like(1) Comments (3) Read more Back from DAC Functional Verification Insights from Austin I just returned back to the office from the 50th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight.... Tags:Functional Verification,Mixed-signal,SoC,SystemVerilog,Training,Verification,Verilog Like(3) Comments (0) Read more Register for Aldec Technical Sessions & Demos at DAC 2013 Advanced Verification, HW/SW Emulation, and more This year’s Design Automation Conference (DAC) will be held in Austin, Texas. If we survive the 70% humidity, our team looks forward to meeting you at Booth #2225 from June 3-5. Aldec HQ is located in Nevada just outside of Las Vegas… so we’re accustomed to more of a dry heat.... Tags:HES,Functional Verification,FPGA,Design,Emulation,Aceleration,ASIC,SoC Like(1) Comments (0) Read more ARM Cortex SoC Prototyping Platform for Industrial Applications Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms, such as Aldec HES-7™, provide a platform for designers to implement and verify functionality of... Tags:HES,Riviera-PRO,Functional Verification,FPGA,Aceleration,Emulation,ARM,Xilinx Like(1) Comments (0) Read more Fast Track™ to SystemVerilog for Verilog Users Aldec’s Latest Free Online Training Many experienced Verilog users tend to ignore SystemVerilog - mainly because high-end verification features of the new language are getting the majority of the attention in the press, and at conferences and trade shows. Those users may not realize that there are many SystemVerilog features that are very useful for... Tags:Riviera-PRO,Functional Verification,SystemVerilog,Verification Like(1) Comments (0) Read more
