Aldec Design and Verification Blog Trending Articles Real-time SDR system with TySOM The Convergence of Emulation and Prototyping Development of real-time SDR systems with Aldec HES Performing cross spectrum video processing on a TySOM-3 board How does the Mars Perseverance rover benefit from FPGAs as the main processing units? SynthHESer - Aldec’s New Synthesis Tool Linting RISC-V designs with ALINT-PRO All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications What inspired you to become an engineer? National Engineering Week is February 22-28 This week, February 22-28, we celebrate National Engineers Week in the US to recognize the contributions to society that engineers make. During this time, there is added emphasis in schools on the importance of learning... Tags:Aceleration,Analog,ARM,Aviation,Co-simulation,FPGA,Functional Verification Like(1) Comments (3) Read more Back from DAC Functional Verification Insights from Austin I just returned back to the office from the 50th Design Automation Conference (DAC) which took place in Austin, TX, on June 2—6. As I began compiling my trip report, I thought that I might share some of my observations, especially for those who couldn’t attend this industry event but still wanted to gain some insight.... Tags:Functional Verification,Mixed-signal,SoC,SystemVerilog,Training,Verification,Verilog Like(3) Comments (0) Read more Register for Aldec Technical Sessions & Demos at DAC 2013 Advanced Verification, HW/SW Emulation, and more This year’s Design Automation Conference (DAC) will be held in Austin, Texas. If we survive the 70% humidity, our team looks forward to meeting you at Booth #2225 from June 3-5. Aldec HQ is located in Nevada just outside of Las Vegas… so we’re accustomed to more of a dry heat.... Tags:HES,Functional Verification,FPGA,Design,Emulation,Aceleration,ASIC,SoC Like(1) Comments (0) Read more ARM Cortex SoC Prototyping Platform for Industrial Applications Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms, such as Aldec HES-7™, provide a platform for designers to implement and verify functionality of... Tags:HES,Riviera-PRO,Functional Verification,FPGA,Aceleration,Emulation,ARM,Xilinx Like(1) Comments (0) Read more Fast Track™ to SystemVerilog for Verilog Users Aldec’s Latest Free Online Training Many experienced Verilog users tend to ignore SystemVerilog - mainly because high-end verification features of the new language are getting the majority of the attention in the press, and at conferences and trade shows. Those users may not realize that there are many SystemVerilog features that are very useful for... Tags:Riviera-PRO,Functional Verification,SystemVerilog,Verification Like(1) Comments (0) Read more Aldec in the Classroom Of Today’s Top Engineering Universities Aldec’s University Program is committed to providing future engineers with world-class tools for their digital system designs and verification methodologies. These tools are offered at a lower cost to educational facilities who meet the university program requirements. In addition, students... Tags:Prototyping,Functional Verification,FPGA,Emulation,Aceleration Like(1) Comments (0) Read more Camouflage for Your HDL Code Designers may deliberately obfuscate HDL code to conceal its purpose (security through obscurity) or its logic, in order to prevent tampering and deter reverse engineering. The obfuscated code is unreadable to the receiving user, but is still readable to compilers and simulators. This way obfuscation also comes... Tags:VHDL,Verilog,SystemVerilog,Functional Verification Like(1) Comments (0) Read more 2012: Emulation's Big Year And a Look Ahead to 2013 2012 was an exceptional year for Aldec globally. The company exceeded revenue expectations across all product offerings, the most significant changes coming from Emulation. Aldec continued to see double digit growth in our traditional market areas of FPGA and ASIC HDL Verification... Tags:FPGA,FPGA Simulation,Functional Verification,SoC Like(1) Comments (0) Read more Interoperability of Project Tasks Between Riviera-PRO and ALINT The Tasks window in Riviera-PRO and ALINT can be used to manage tasks that need to be completed in the design. Tasks can be anything that a user would like to address later in the project. In a team-based environment where multiple engineers are working with different aspects of the same design... Tags:Design,Functional Verification Like(1) Comments (0) Read more Those Pesky SystemVerilog Interfaces... SystemVerilog introduced numerous ideas new to Verilog programmers. Some of them enhanced hardware descriptions (e.g. always_ff block), some were meant to enhance verification (e.g. classes) and some were cross-over enhancements that can be used in many different contexts. SystemVerilog interface... Tags:Functional Verification,Riviera-PRO,SystemVerilog Like(1) Comments (0) Read more
