The User:

Xelic, an OTN IP Core and Subsystem provider, required:

• SystemVerilog-based simulation capability with:

- UVM support
- Coverage driven constrained random methodology   support
- Functional Coverage
- Code Coverage
- Assertions
- GUI interface for debug
 

• Reasonable simulation performance

• Vendor library support (mainly FPGA)

• Mixed-language support for legacy VHDL/Verilog environments as well as VHDL-only (design and verification)

• A practical licensing price point to support development (mini regressions, GUI, and batch jogs)  along with production release to include full multi-seeded batch regressions and coverage

How Aldec Delivered:

• Mixed language support VHDL/Verilog

• Pure VHDL support

• SV/UVM support

- Constrained Randomization
- Functional Coverage
- Code Coverage
- Assertions

• Vendor library support for Altera and Xilinx

• Powerful GUI for development and debugging

• Multiple levels of optimization for performance tuning

• Responsive tech support that delivered productivity enhancing tips/techniques

• Reasonable cost for competitive performance

• Ease of operation with third party/in-house queue manager