Testimonials

Auburn University
We use Active-HDL as the main simulator  to teach VHDL language in our "Digital Technique" course. Our students found this tool to be friendly and quite easy to use, particularly in learning VHDL language. I and my colleagues think Active-HDL is the best system to learn VHDL very quickly. We can find all what we need, ranging from a dedicated editor and fast compiler to final simulator and presentation tools. The big advantage of this software is possibility to use it as a main system in the future professional activity, especially with reference to modern FPGA circuits.

Military University of Technology
We use Active-HDL as the main simulator  to teach VHDL language in our "Digital technique" course. Our students found  this tool to be friendly and quite easy to use,  particularly in learning VHDL language. I and my colleagues think Active-HDL is the best system to learn VHDL very quickly. We can find all what we need, ranging from a dedicated editor and fast compiler to final simulator and presentation tools. The big advantage of this software is possibility to use it as a main system in the future professional activity, especially with reference to modern FPGA circuits.

Dr. Zbigniew Jachna, Assistant Professor, Department of Electronic Engineering

The Hong Kong Polytechnic University
“The Department of Electronic and Information Engineering has been using Aldec's Riviera-PRO for teaching and research since 2011. The intuitive GUI makes it very easy to use and students need very little guidance.  One of the most powerful features is its integration with up and downstream EDA tools. Riviera-PRO is tightly integrated with High-Level Synthesis tools  also used at the department and all major FPGA vendors' tools, making it extremely easy to build a complete flow from design to prototyping around Riviera-PRO.”

Dr. Benjamin Carrion Schafer, Assistant Professor, Department of Electronic and Information Engineering

"I have used Aldec tools both professionally and academically for over a decade. There is not a comparable software program for digital design that provides both the simplicity and flexibility of ActiveHDL."

Michael Anderson -  Professional Engineering & University Professor

University of South Florida
“We use Riviera-PRO as the main simulator in our courses VHDL (EEL 6935) and Rapid System Prototyping with FPGAs (EEL 6936). The tool has proven to be  easy to learn and very flexible and powerful. Our students consider the HDL editor very friendly and convenient because of the syntax highlighting, the text formatting and the wizards to generate code templates. One of the most used features is the generation of test bench templates. We recommend it as a tool to teach Hardware Description Languages (VHDL and SystemVerilog).”

Dr. Jorge Galvis, Professor of Electrical Engineering

Rowan University
"The Computer Science Department moved to Active-HDL as part of an initiative to introduce and teach Hardware Description Languages (VHDL) into the computer science curriculum for computer architecture and computer hardware that will benefit from Active HDL design.

We as Computer Science professionals and educators are always looking for effective means to facilitate learning and provide the "state of the art" experiences for our student. Your product provides just such an environment for our undergraduate hardware centered classes. We and our students have found Active-HDL to be a very versatile and an easy to use environment for developing digital components and systems. Further, our students find the ability to manage and test complex designs very helpful in removing the burden of learning a development environment from the design process. We believe that our students must be versed in both the hardware and software aspects of our profession to be relevant to a changing job market. Active-HDL and the integration of VHDL into our computer architecture course sequence provides the opportunity to our students to develop a deeper understanding of digital design and computer hardware. The built in documentation and wizards also eases the burden of learning the tool and the support that Aldec provides for this product is outstanding. I would recommend Active-HDL to any faculty, students or university looking to move forward with a design and simulation tool that allows more time to be devoted to learning computer hardware and digital design."

Dr. Nancy Tinkham, Professor and Chair, Computer Science Department

University of Nevada Las Vegas
"I use Active-HDL to teach Hardware Description Languages (CPE410 and EE610) in our University. Active-HDL is an Electronic Design Automation tool which is tailored to the needs of all designers using Programmable Logic Devices. I found Active HDL to be the best tool to teach VHDL. It is very user friendly, easy to use and versatile. My students find the on-line-documentation to be very useful. The language assistant and the wizards help in writing the code very quickly. I am appreciative of the customer support that is prompt and accurate. My graduate students who are designing an image processor find this tool more efficient than other tools for simulation and debugging. I would recommend Active-HDL to both students and designers.”

Dr. Henry Selvaraj, Professor and Chair Department of Electrical and Computer Engineering

AGH University of Science and Technology
"We have been using Aldec's Active-HDL for teaching for over 10 years. Beginners like this tool for its ease of use, clear user interface and seamless integration with FPGA vendors tools, which allow to focus on the HDL matters while learning. Advanced students appreciate the fast mixed-language simulation and a wide set of resources. All this make the Active-HDL a perfect tool for a wide spectrum of our digital design courses, as well as for final projects."

Pawel  J. Rajda, PhD EE 

Auburn University
For the past two years, we have used Aldec Active-HDL in our junior/senior-level digital systems design courses for VHDL modeling and simulation, with at least one design also developed using Verilog.  In the lab sessions of this course, students implement and test designs on Xilinx FPGAs. They typically create their HDL behavioral or RTL model in the Xilinx ISE tools, from which initiate simulation to verify the model. After verification of the design’s behavior, they go through the process of synthesis, map, place and route to implement the design on the FPGA, and then simulate the final structural model to verify that it produces the same behavior as the initial model, and that it’s timing is acceptable. 

We have found that Aldec Active-HDL works seamlessly with the Xilinx ISE tools. Active-HDL simulations are launched from within ISE, with the Active-HDL project created automatically.  Students have found the Active-HDL simulation tools easy to use, both for creating stimuli for design inputs and for studying simulation results.  In addition, students have found the Student Edition to be helpful outside of lab to help create and test HDL designs before coming to their lab sessions. We have also found that Active-HDL makes the transition between VHDL and Verilog modeling relatively straightforward. We look forward to continuing to work with these excellent tools from Aldec.

Victor P. Nelson, Professor and Assistant Chair, Electrical and Computer Engineering