Aldec Design and Verification Blog
Trending ArticlesIn this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ...
For the past several years I have had the privilege to chair the IEEE 1076 VHDL working group. In March we handed off the revisions to the VHDL LRM to our technical editor to finalize the document for balloting. As we are waiting for the standards process to finish up, I thought I would share my favorite new additions. Let me start with an executive summary: ...
Here at the Aldec corporate office, we have a sign that reminds us all of our mission in the field of Technology. It reads, ‘To deliver solutions that provide the highest productivity to value ratio;...
As the proud Product Manager of Aldec’s FPGA Design Simulation solution, I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997....