Aldec Design and Verification Blog Trending Articles Navigating VUnit: A Practical Guide to Modifying Testing Approaches Speeding Up Simulation with VUnit for Parallel Testing Introduction to VUnit FPGA Design Verification in a Nutshell Versal ACAP Simulation Challenges Real-time SDR system with TySOM The Convergence of Emulation and Prototyping All Categories Corporate DO-254 Compliance Embedded Solutions Emulation/Acceleration FPGA Design Functional Verification High Performance Computing Requirements Management SoC and ASIC Prototyping SoC Design and Validation Specialized Applications Verification Effectiveness with Riviera-PRO: SystemVerilog Randomized Layered Testbench Understanding SystemVerilog Layered Testbench In this blog, I will discuss randomized layered testbenches used in SystemVerilog. We need to understand why we need it, ... Tags:Riviera-PRO,ASIC,Assertions,Co-simulation,Coverage,Debugging,Design,Documentation,FPGA,HDL,IEEE,OS-VVM,Randomization,Simulation,standards,SystemVerilog,UVM,Verification,Verilog Like(4) Comments (0) Read more VHDL-2017: Some of My Favorite Things For the past several years I have had the privilege to chair the IEEE 1076 VHDL working group. In March we handed off the revisions to the VHDL LRM to our technical editor to finalize the document for balloting. As we are waiting for the standards process to finish up, I thought I would share my favorite new additions. Let me start with an executive summary: ... Tags:HDL,IEEE,Simulation,Verification,VHDL Like(4) Comments (0) Read more It’s no accident that Aldec offers the best VHDL-2008 support Tools, Resources and Training for VHDL Users Here at the Aldec corporate office, we have a sign that reminds us all of our mission in the field of Technology. It reads, ‘To deliver solutions that provide the highest productivity to value ratio;... Tags:HDL,IEEE,Simulation,standards,Verification,VHDL Like(3) Comments (0) Read more 90’s Kid Active-HDL Celebrates Sweet 16 Serving FPGA Designers as the tool of choice since, like, forever As the proud Product Manager of Aldec’s FPGA Design Simulation solution, I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997.... Tags:Assertions,Co-simulation,Coverage,Debugging,Design,Digital,Documentation,FPGA,HDL,IEEE,Matlab,OS-VVM,Simulation,standards,university,Verification,Verilog,VHDL,Xilinx Like(2) Comments (2) Read more
