Aldec Design and Verification Blog

Trending Articles
90’s Kid Active-HDL Celebrates Sweet 16
Serving FPGA Designers as the tool of choice since, like, forever

As the proud Product Manager of Aldec’s  FPGA Design Simulation solution,  I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997....

Like(2) Comments (2) Read more
Working Smarter not Harder
To Accelerate DSP Design Development

If we’re being honest, human beings, especially engineers, are lazy. Let’s face it, most inventions ever made were created for the sole purpose of making our lives easier. The same goes for the manner in which we create our designs....

Like(4) Comments (0) Read more
Ask Us a Question
x
Ask Us a Question
x
Captcha ImageReload Captcha
Incorrect data entered.
Thank you! Your question has been submitted. Please allow 1-3 business days for someone to respond to your question.
Internal error occurred. Your question was not submitted. Please contact us using Feedback form.
We use cookies to ensure we give you the best user experience and to provide you with content we believe will be of relevance to you. If you continue to use our site, you consent to our use of cookies. A detailed overview on the use of cookies and other website information is located in our Privacy Policy.