Documentation

Application Notes Starting Active-HDL as the Default Simulator in Intel® Quartus® Prime Loss of Menu Items and other GUI Misbehavior when Using Active-HDL Collecting Code Coverage in Active-HDL Enhancing VHDL Testbench Using Matlab® Interface Installation of Pre-compiled Vendor Libraries for Riviera-PRO Selecting Default Waveform Format in Active-HDL Importing ModelSim® Project Starting Riviera-PRO as the Default Simulator in Intel Quartus® Prime How to Simulate Designs in Active-HDL Using CVS Source Revision Control with Active-HDL HDL Debugging in Active-HDL Modelsim's® SignalSpy functionality migration to SignalAgent in Aldec's simulators Xilinx System Generator with Active-HDL Using Components from Any Design’s Library by making the Library Global Recompiling System Libraries Compiling Multiple SystemC Libraries Active-HDL Interface to Simulink® How to Use Xilinx Constraints in Active-HDL Using Advanced Dataflow Time Calculations in VHDL Installing and Simulating Xilinx SmartModels in Active-HDL Importing Active-CAD designs in Active-HDL Getting Started with Active-HDL Batch Mode File Management with Relative Paths in Active-HDL Enhancing Verilog Testbench Using Matlab® Interface Starting Active-HDL as the Default Simulator in Microchip Libero Using Protected Types in VHDL Designs Saving Waveform and other GUI preferences in Riviera-PRO SVN Installation and Use with Active-HDL Source Revision Control Simulating ALTERA NIOS II Embedded Processor Designs in Active-HDL Obtaining Machine lmhostid on Windows, Linux and Unix Managing your Waveforms through the Command Line Getting Started with Active-HDL Installing a new FLEXid=9 USB keylock and drivers - Obsolete Changing the name (title) of the waveform windows in Riviera-PRO Native Support for FPGA Primitives in ALINT Using ALINT with Aldec and Third-Party Simulators Phase-Based Linting Methodology Starting Active-HDL as the Default Simulator in Xilinx ISE Starting Riviera-PRO as Default Simulator in Xilinx® ISE Design Suite Using NC-Verilog® Verilog-XL® scripts in Riviera-PRO Simulink® Interface in Riviera-PRO Matlab – HDL Interface in Riviera-PRO and Active-HDL Simulating Xilinx MicroBlaze design using the Active-HDL Simulator Disabling Elaboration on Design Loading in Active-HDL Simulating AXI-Based Systems Created Using Xilinx Platform Studio Simulating AXI BFM Examples Available in Xilinx CORE Generator Integration of ALINT with Active-HDL Integration of Riviera-PRO with Active-HDL Language Neutral Libraries with Microsemi® Language Neutral Libraries with Altera® Language Neutral Libraries with Xilinx® Compile Xilinx ISE Libraries for Aldec using compxlib Simulating Xilinx MicroBlaze design in Riviera-PRO Simulator Mouse Strokes Creating Multiple Symbols for One Library Unit User-defined Design Management How to compile Active-HDL libraries in Altera Quartus Supported VHPI Functions VHPI Applications Controlling Riviera-PRO from MATLAB® Using Agilent SystemVue® Co-Simulation Interface Setting up Source Code Analysis for SystemVerilog Compilation Using Toggle Coverage Debugging C/C++ Applications FPGA_PROG and PROM Chips Configuration on the HES7XV690-4000BP Board SW2 DIP Switch and LED1-8 bar LEDs on the HES7XV690-4000BP Board 7-Series FPGA Chips Programming on the HES7XV690-4000BP Board Diagnostic Design Configuration and Testing Using hes7proto.exe on the HES7XV690-4000BP board Managing To-Do Tasks Scheduled in a Project Creating and Customizing Design Policies Creating and Linting a Design in ALINT Creating a Script for Batch-Mode Linting Using virtualization to save and restore Active-HDL simulation Using Team Foundation Server with Active-HDL Starting Riviera-PRO as the Default Simulator in Xilinx Vivado 2017.3 or Earlier Starting Active-HDL as the Default Simulator in Xilinx VIVADO™ Xilinx AXI-Based IP Overview HDL Code Obfuscation Interoperability of Project tasks between Riviera-PRO and ALINT Virtual Signal Expressions in the Waveform Setting a Breakpoint on a particular Class instances Simulating AXI-based Designs in Active-HDL Interoperable Encryption of HDL Intellectual Property Simulating AXI-based Designs in Riviera-PRO Simulating a Design with Xilinx Libraries (UNISIM, UNIMACRO, XILINXCORELIB, SIMPRIMS, SECUREIP) Compiling Xilinx™ Vivado Simulation Libraries for Riviera-PRO Performing Functional Simulation of Xilinx™ Zynq BFM in Riviera-PRO Performing Functional Simulation of the system created with Qsys in Riviera-PRO Performing Functional Simulation of the system created with Qsys in Active-HDL Simulating Nios® II Designs in Riviera-PRO Using Stimulators with the Accelerated Waveform Viewer in Active-HDL Memory Initialization using HesDebug API from HDL testbench in Acceleration Mode Setting up ALDEC License Server Block-level design constraints in ALINT-PRO Combining Code Coverage and FSM Graph in Riviera-PRO to extract FSM debug information Time and Date Operations Using virtualization to save and restore a simulation Working with ASDB and AWC files in Active-HDL Getting started with UVVM using Riviera-PRO Getting started with ALINT-PRO Compiling Altera Quartus Simulation Libraries for Riviera-PRO Migrating ALINT Designs and Settings to ALINT-PRO Starting Active-HDL as the Default Simulator in Intel Quartus II Basic use of SystemVerilog DPI-C in Riviera-PRO Compiling Intel Quartus Simulation Libraries for Riviera-PRO Getting started with OSVVM using Riviera-PRO. Using Riviera-PRO in Batch mode using Jenkins Software-Github Collaboration Using Cocotb for design re-use and randomized testing in Riviera-PRO Accelerating Simulation of Vivado Designs with HES Customizing Linting Policy Using Waivers to Skip Irrelevant Violations Installation and Licensing UVM based Verification using Riviera-PRO Getting Started with ALINT-PRO Batch Mode Setting Up Linting Regressions Chip-Level Design Constraints in ALINT-PRO Starting Riviera-PRO as Default Simulator in Xilinx Vivado Linting with ALINT-PRO within Active-HDL Getting Started with Active-HDL in Diamond Getting Started with Radiant Automated Conversion of Xilinx Vivado Projects to ALINT-PRO Automated Conversion of Intel FPGA Quartus Projects to ALINT-PRO Using Riviera-PRO in Batch mode using Jenkins Software for Linux Best-Practices in Speeding Up Design Linting of Large Designs Verifying CDC Reconvergence Issues with ALINT-PRO Gitlab - Riviera-PRO integration Code Coverage Visualization in GitLab HW/SW co-simulation solution for Zynq SoC based systems using RIVIERA-PRO and QEMU Compiling Intel® Quartus® Simulation Libraries for Active-HDL Starting Riviera-PRO as the Default Simulator in Intel Quartus® Prime Starting Active-HDL as Default Simulator in Xilinx Vivado Compiling Xilinx Vivado Simulation Libraries for Active-HDL Starting Active-HDL as the Default Simulator in Microchip Libero Starting Riviera-PRO as the Default Simulator in Microchip Libero Active-HDL and GOWIN Flow Installing a new FLEXid USB keylock and drivers Automated Conversion of Microchip Libero projects into ALINT-PRO Active-HDL Simulator Options in Vivado Riviera-PRO Simulator Options in Vivado GitLab Instance Installation and Configuration Performing Functional Simulation of the system created with Platform Designer in Active-HDL Performing Functional Simulation of the system created with Platform Designer in Riviera-PRO Demonstration of Riviera-PRO and GitLab Integration in Docker Based Environment Using Docker with Riviera-PRO	FAQ Compiling altera_primitives.v (Quartus 11.1) in Riviera-PRO and Active-HDL Add file for simulation without manually adding the file to design. Hierarchical Mode in Advanced Dataflow Window Empty Library Manager Does the simulator have the capability to save the results of one or more outputs into a text file? Does the Aldec simulator have hierarchical referencing similar to ModelSim's Signal Spy? Does Active-HDL Plus Edition (PE) include Code Coverage? Does Active-HDL support 64 bit Windows7? Dynamic Memory Allocation Problem How to change the font size in waveform viewer? How do I apply the new license file of Active-HDL to my existing node-lock license? Text Find Stops Working Saving Waveform Specifications Disabling Elaboration on Design Loading in Active-HDL Disable VHDL Optimization Warning Message Disable IEEE Warnings Convert Waveform from Standard Waveform Format to Accelerated Waveform Format What is the difference between a Vital Model and Vital Library? ELBREAD: Error: The contents of entity '' instantiated in architecture '' differ from the contents available during the compilation of this architecture Is my license backwards and forward compatible? Entry and Exit Actions in the FSM Editor Error when Attempting to Install Libraries Generating Compilation Script How do I hide or show items such as ports or text box in BDE file? Gray Mode in Advanced Dataflow Window Analog Waveform Display ASDB Server Error Assigning Pin Numbers in Block Diagram Editor Cannot Debug Source Code. Cannot Set Breakpoints. Can I use Terminal Services with Active-HDL? Can Quartus II Power Input File be generated with Active-HDL or Riviera? Cannot Select Top Level How can I hide processes inside Structure tab of the Design Browser? Multiple State Machines on one Diagram. Trace window in Advanced Dataflow Why does tcl variable ($argv0) display curly brackets at console window during second run? Can I disable the compile time warning messages in the command line? Concatenation in VHDL Code2graphics in Active-HDL Desktop Master version Code Generation Settings for State Machines Delta Count Overflow Comment and Uncomment Block Concurrent Simulation on a Multi-Core CPU Machine with Active-HDL Customizing Waveforms to Suit Your Own Needs Design Browser and Structure Window Pane Disappeared Saving Simulation Waveform Design Flow Manager Disabled Can I put some of my many modules in Hardware and additional modules later without having to re-compile? What is the hardware capacity supported by HES? What languages does HES support? Active-HDL Upgrade How not to capture Simulation Data during a specified simulation duration Interaction between Waveform Viewer and Advanced Dataflow During Simulation Can I use HES with a 3rd party simulator? DllRegisterServer error during Installation What type of performance increase should I see when using HES? Best PC configuration for Active-HDL Xilinx .fdo File and Signal Radix Working with IBM Rational ClearCase Version Control Tool Stimulators disappearing from waveform Xilinx Foundation schematics support. Deleting Design files Launching Active-HDL from Lattice ispLever. Is there any advantage in terms of simulation speed to use “signed”, “unsigned”, or “integer” types? Launching ModelSim from Active-HDL How to disable License Configuration Window during Active-HDL startup? Error: VCP0120 Internal unknown error occurred. Error: COMP96_0607: .vhd : The signal used as the actual parameter in a subprogram which is not a formal parameter of that procedure. Different Ways of Creating Waveforms Ambiguous Subprogram Active-HDL License Error: Cannot read data from license server system Active-HDL Does not Start after System Clock Time Change What is the best PC Configuration for Riviera-PRO? Warning: KERNEL_0085 does not have read access. Use switch +access +r for this region What type of ARM processor does HES support? What platforms are supported by HES? IEEE Library Warnings Warning : FSM2HDL_3127 ..asf : The default state is not empty, the coverage pragma has been omitted. Verilog Compilation Error Watch Window List Viewer or Delta cycle Window USB dongle and Windows 7 support Unknown VHDL Compilation Error with Daggen VHPI Programing Unable to Install Active-HDL with no related activity showing in Task Manager Unable to Install Active-HDL Trap State How to switch between two node locked licenses without always copying license.dat file? How to add primitives and IP cores from Xilinx to Active-HDL? Disable Timing Check Message during Timing simulation using Design Flow. How to check detailed Simulation Delay File (SDF) annotation report when doing the timing simulation? Active-HDL Installation on Windows 64 bits. Error: COMP96_0234: Fatal error : INTERNAL COMPILER ERROR (compiled file "(file path)" - semantic process) Unresolved hierarchical reference to"glbl.GSR" VHDL Compilation Standards Standalone Accelerated Waveform Viewer (ASDB) What software/hardware comes with HES? Which debugger is supported by HES? How do you instruct the simulator not to generate X values? Specifying Verilog Library for Compilation Simulating and Debugging State Diagrams Graphically Signal list disappeared after simulation initialization Show Event Source Setting Signal Breakpoints Setting License variable for CADSTAR Shared variable not a protected type Revision Control Software supported by Active-HDL Port Declaration Orders Port Assignment for FPGA/CPLD Chip Parallel Dongle Based License Add BDE/ASF generated code to Source Revision Control Disabling No license for Verilog Performance Optimized Simulation Message No Code Coverage Data in results.ccl How to add library module to an existing library? How do I set the grid length in the waveform viewer to a number that is not an integer such as 5.208333 ns? Page Order of a Multi-page Block Diagram Internal Compiler Error Modifying Signal Columns in the Waveform Viewer Library STD not Found Is there a way to Change the Color Scheme of the Design Browser in Active-HDL? Is there any way to disable updating console.log file during simulation with a macro command? Is it possible to run Active-HDL in command line mode with Lattice Edition? Is there a way for Active-HDL waveform editor to read from an input file directly? Invalid Hierarchical Access How to create new symbol or bde file from a existing ones? Is it possible to run Active-HDL on a remote machine with a node locked license? Incremental Service Pack (SP1, SP2, etc) Does Not Install Incompatible Format of Standard IEEE Library Can I import an existing schematic developed in Viewlogic into Active-HDL? How to set delays on sampled signals in Active-HDL? How to turn off writing to console.log in Active-HDL? How to set an environment variable using VHDL code? How to run scripts without loading design? How to set a pin as open using the block diagram editor of Active-HDL? How to properly install Active-HDL 8.3 license with usb dongle when I get USB dongle error? How to open VSIMSA in Active-HDL or Riviera-Pro if you have installed both tools? How to open and make changes to a legacy Active-CAD design ? How to change and save preferences for waveform colors? How to make a copy of generated source file besides compile folder? How to move my personal preferences from one installation of Active-HDL to another? How to display the names of nets in the BDE file? IEEE Library Package Changed Does Riviera-PRO create core dump file? Forcing Signals and How to Stop it Selecting Columns Supported File Types How to close Waveform Viewer using TCl script in Active-HDL? How to create a new VHDL library? How to change the name of an Active-HDL design? How to change the entity name generated from .bde file? How to add Error and Warning tabs to console window? How do I stop the simulation when a VHDL assert statement fails? How do I make Waveform background black in AHDL? How do I enable ModelSim compatibility mode? How do I change between the standard and accelerated waveform viewers? How can I restore a .BDE file from its .BAK file? How can I know whether I have installed a particular service pack or not? Cannot Open Configuration Subprograms in VHDL Adding to Memory Viewer from Structures Window How Can I obtain a 20-Day Unrestricted Evaluation License? Hierarchical State Machines Compxlib in ISE 13.3 errors out when simulator is set to Riviera-PRO DO-254 CTS – Frequently Asked Questions Will my designs created in an older version of Active-HDL work in the new Active-HDL? Licensing and Download Why Does My License Expire? I received a license file by email from Aldec - Is this all I need for the software to work? How to use a CSV file in an FSM so you can use user defined codes Floating License Installation on Linux/Unix USB cable is not detected when using iMPACT invoked from Active-HDL Is there an equivalent to Questa's signal_spy functionality? Warning: Cannot trace SLP signal in standard Waveform module. Please use Accelerated Waveform Viewer instead. #ELBREAD: Warning: Module '' does not have a `timescale directive, but previous modules do. Floating License Installation on Windows Can I customize my keyboard shortcuts in Active-HDL? When the waveform background is dark, the expandable triangle for buses and virtual groups is not visible. Would it be possible to change the color of the triangle to make it more visible? What does message: "# No signals matching" mean? Design Browser Window Disappeared How to create a new Xilinx core VHDL library and compile related files? How do I set an external text editor program as the editor for coding in Active-HDL? Error while loading shared libraries: libtyphoon.so:cannot restore segment prot after reloc:Permission denied How to exclude the file from a coverage report How to execute system commands from the Active-HDL console How to install Active-HDL in unattended(silent) mode Kernel Memory Leak when simulation is initialized on ClearCase dynamic view Kernel Memory Leak when simulation is initialized on ClearCase dynamic view Slow simulation with Accelerated Waveform Viewer Can we use a standard PC power supplier for powering the HES7 board? Can I configure the USB and PCIe, what about the ethernet? Can I use two PCI-Express simultaneously? Can the Kintex-7 device on the board be used for Prototyping, in addition to the Virtex-7 devices? Does HES-7 interface with the ARM processor Core Tile daughter cards? Do you include test designs so I can confirm that the board is working as expected when delivered? Do you support ChipScope and other third-party debuggers and logic analyzers? Are there any short circuit protection or voltage supervisor circuitry? Can we use our lab power supplier for powering the HES7 board? Is there any programming sequence for FPGA chips required? How to connect a HAPS Daughter Board with a Samtec Connector? How to access the HES-7 board from my company’s secured lab of hardware? How much external memory is supported? I'm partitioning my design in two partitions, how many interconnections between V7 chips do I have in HES-7, can I use GTX too? How many DDR sockets are available on the HES7 board? How many clock modules are available on the HES7 board? How did you calculate and determine that I have access to 24 million ASIC Gates? How can I program Kintex-7 and Virtex-7 chips on the HES7 board? How can I configure onboard PROM memory connected to a Spartan-6 chip? How can I configure FPGA clock input frequencies? What is the maximum speed of the GTX connections? What is the required voltage rating for the power supply voltage? What is the recommended power supply connector? What is the recommended power supplier for HES7XV690-4000BP boards? What is the recommended PCI-Express Cable for PCI-Express cable connection? What is the recommended FPGA chip configuration method? What is the recommended configuration cable for HES7 JTAG programming? What is the purpose of the S2 DIP switches? What is the purpose of the S1 Tact switch? What is the power consumption of the HES7XV690-4000BP boards? What is the Hardware Warranty for HES-7? What is the default clock module configuration? What if a too-weak power supply source is used? What does it mean when the red LEDs are turned on? What are “TP” points for? What are the recommended Power Supply conditions? What are the two green bar LEDs (marked as LED1 and LED2) on the PCI-Express bracket for? What are the D2-11 LEDs (under the Power supply chips) for? Which type of Sata mode (HOST/DEVICE) is supported on the HES7 board? Which FPGA chips are connected to USB interfaces? Which connector should I use for Spartan-6 chip programming? Which connector should I use for 7-series chip programming? Which connection modes (HOST/DEVICE) are available on the HES7 USB interfaces? Where can I measure clock frequencies, are there any clock test points? When should I use the S1 tact switch? What parameters should be set while programming JTAG chains? What should I do when the board is not booting up after power up? What clock frequencies can be set in the clock modules? What type of DDR memory is supported? What should I do to switch between Finger and Cable PCI-Express connectors? What kind of clocks is the HES7 board equipped with? Why are the JTAG interfaces for Spartan-6 and big 7-series FPGA chips separated? How to check out a specific license for Riviera-PRO if there are multiple configurations Error: Design unit not found in searched libraries: Error: Design unit not found in searched libraries: Error: VCP6251 Error in SLP repository: Unknown repository object type How to record all messages displayed in the Riviera-PRO Console to a log file Language Neutral Simulation of Altera IP cores in Active-HDL Language Neutral Simulation of Altera IP cores in Riviera-PRO What comes packaged with the HES-7 system? ELBREAD: Error: You do not have a valid license to run VHDL simulation How do I disable a given warning during Verilog compilation? ERROR VCP2000 "Syntax error. Unexpected token: library[_IDENTIFIER]. Expected tokens: 'function' , 'task' , 'timeprecision' , 'timeunit' , 'const' ... ." How do I use code coverage in the command line? Error: E8017 : Internal application error - please contact Aldec support - support@aldec.com RUNTIME: Fatal Error: RUNTIME_0048 : Cannot open file "filename"; no such file or directory SLP: Fatal Error: elab_on_old_tree.cpp (1958): Internal fatal error F5.1958 WARNING VCP2822 "Incompatible types at task enable/function argument" VLM ERROR VLM_0037: "Package "ieee.numeric_std_unsigned" is not accessible in -93/-2002 mode." SLP Fatal Error: hier_refs.cpp (700): Internal fatal error FSM format change: Invalid file format. Cannot load file .asf BDE format change: This file was created in a version later than 9.2.2499.4581.01 and it cannot be read in version 9.2.2499.4581.01 Does HES-DVM support Xilinx ChipScope PRO Debugging Tool? Does HES-DVM include any tools for prototyping? Does HES-DVM provide a scripting interface? Does HES-DVM support FPGA Hard-Marcros? What is group synthesis? What is incremental synthesis? How are both used in HES-DVM? What type of debugging capabilities is available for emulation? How do you build a job queue for running emulation using HES-DVM? Can I submit the emulation jobs without the manual control? Please advise how to build multi-user environment for HES emulation. Is it possible to change how much of the FPGA is utilized during the partitioning process of my design in HES-DVM? Is it possible to run parallel tasks during implementation stage of HES-DVM to speed up implementation time? I have EDIF net lists in my design, how do I use these files in HES-DVM How do I download the bit files compiles from HES-DVM in HES-proto mode? How does HES-DVM handle simulation memory models? How does HES-DVM handle gated clocks in my design? In HES-DVM, is it possible to select any of the probes in RTL signal name in the HW debugger? Or is it necessary to link Riviera-PRO or Verdi server to have full visibility of RTL signal for the selection of probes? In HES-DVM, there are many factors which will be taken into the consideration to decide the maximum achievable runtime speed? The maximum delay in the data path reported/analyzed by Xilinx tools is one those factors. Is HES-DVM able to modify timing constraints automatically generated for P&R implementation process? In the HES-DVM generated SystemC wrapper, there are some interface signals which are not in the list of I/O signals of DUT, what is the purpose of these signals? Which SCE-MI interface does HES-DVM support? How do I change the Verilog timescale for the HES-DVM generated wrapper file? What synthesis tools are supported in HES-DVM? Node-locked License Installation on Windows Does Spec-TRACER support IBM Rational DOORS? Does Spec-TRACER need to go through the tool qualification process for DO-254? Does Spec-TRACER offer Impact Analysis? Does Spec-TRACER provide traceability to HDL design and testbench files? I am the project manager in our organization and I have several team members involved in the project. Does Spec-TRACER support team-based methodologies? Do I need to run a simulation using Active-HDL in order for Spec-TRACER to track and trace to the simulation results? How can Spec-TRACER help in the review process of requirements? What are the database formats supported by Spec-TRACER? How can Spec-TRACER help me obtain DO-254 compliance? What is the integration of Spec-TRACER to Active-HDL? What is the integration of Spec-TRACER to Mentor's Questa® and ModelSim®? What are the system requirements for Spec-TRACER? What is the DO-254 guidance regarding requirements traceability? What file formats can I import into Spec-TRACER? What is the main functionality of Spec-TRACER? What is the integration of Spec-TRACER to Riviera-PRO? License error: Invalid hostid on SERVER line Warning: KERNEL_0085 does not have read access. Use switch +access +r for this region Why does my library size increase every time I recompile the same design, even if I don’t change anything? [BDE] Error loading the file, error in .cpp file How to enter values for signal breakpoints ELBREAD: You do not have a valid license to run simulation with SLP Is the data compatible between the Riviera-PRO 32-bit version and the Riviera-PRO 64-bit version? ELBREAD: Error: You do not have a valid license to run a Verilog simulation "Browser.dat could not be opened" error during Active-HDL installation ACOM: Error: COMP96_0153: Formal "" of class variable must be associated with a variable ACOM: Error: ELAB1_0021: filename.vhd: Types do not match for port "port_name" Fatal Error: ELAB2_0056 Port '' not found Error: VCP2505 : Duplicate identifier: Error: COMP96_0071: Operator "" is not defined for such operands How can I debug a delta count overflow? Error: COMP96_0078: Unknown identifier "identifier_name" Fatal Error: filename.sv: Bind: unresolved hierarchical reference to object "object name" How can I disable the following message: # KERNEL: WARNING: NUMERIC_STD."=": metavalue detected, returning FALSE? Error: COMP96_0115: Actual is not a globally static expression Error: VCP2562 : Redeclaration of port How to display the time in batch mode simulation Error: ALOG: Cannot add data to library How do I stop the following warnings? #KERNEL: WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es) KERNEL: Fatal Error: System exception occurred: SIGSEGV - cannot continue after such error SCRIPTER: Error: Incorrect syntax: workspace.create Active-HDL Lattice Edition How to calculate average frequency of edges between two events on the waveform ELBREAD: Error: You do not have a valid license to simulate SystemVerilog assertion module I installed a new version of Active-HDL and my design flow manager settings are removed? How do I restore them back? How do I move my design flow manager settings from a previous version of Active-HDL to a new version of Active-HDL? Why am I getting # Warning: Diagram structure inconsistencies encountered when opening "<path>\<filename>.bde". # Inconsistencies have been removed during loading and file has been marked as modified. Why my license does not work with Active-HDL 10.1? Why my license does not work with Active-HDL 11.1? Components of XilinxCoreLib Library Are Missing after Migration to Xilinx Vivado Synopsys/Microsemi Licensing Issue in Design Flow Manager “Active-HDL not installed” message when running library installer How can I compare Coverage Results from one simulation run to another? In the BDE editor, multiple nets change name after I modify one of them Using ACDB report with wildcard Active-HDL HDL Editor shortcut assignment How to detect if script is running in GUI SCV Library extensions in Riviera-PRO Sources not found when organizing files into folders Greyed out Active-CAD option on install Compiling sources into different libraries in Active-HDL Merge Coverage Reports in Active-HDL GUI Does Signal Agent Support VHDL Record Types? How do I convert my item codes list to plain text in MS Word? How to Obtain MAC Address What are the system requirements for Spec-TRACER?	Manuals ALINT Manual Message Reference (MSGREF) Riviera-PRO Active-HDL Manual ALINT-PRO-CDC Manual Riviera-PRO Manual ALINT-PRO Manual
White Papers Automated ASIC Regressions With Aldec Server Farm Manager HDL Simulation And Mathematical Modeling Integration Concurrent FPGA-PCB Design within an Integrated Design Environment Embedded Systems Verification Enhancing Verilog Designs with Embedded PSL Enhancing Verilog Designs with SVA Enhancing VHDL Designs with Embedded PSL System Level Design - SystemC Using Transaction Level Modeling Tool Assessment and Qualification with the Aldec DO-254 Compliance Tool Set Using FPGA Based Simulation Acceleration in Typical ASIC Design Flow Verification of Ethernet Designs with SCE-MI based Aldec Emulator Using FPGA Prototyping Board as an SoC Verification and Integration Platform Meeting Growing Verification Demands Interoperable IP Delivery Simulation Acceleration with HES XCELL Virtual Modeling with Aldec and Imperas Clarifying Language Methodology Confusion Introducing Transactions In Design Verification Debugging SCE-MI Co-Emulation in Riviera-PRO Superior Approach to DO-254 Hardware Verification Randomization and Functional Coverage in VHDL DO-254 Tool Qualification Process Guidance for Active-HDL Code Coverage Vector Implementation of Integer Arithmetic in VHDL Q&A with FAA DO-254 DER Randall Fulton ASIC Prototyping - co-authored with Xilinx Corporate Standardization of FPGA Design Flow DO-254: Increasing Verification Coverage by Test Those Pesky Interfaces… Best Design Practices for High Capacity FPGA Devices Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms Making Floating-Point Arithmetic Work in Your RTL Design ARM Cortex SoC Prototyping Platform for Industrial Applications DO-254 Requirements Traceability Accelerate SoC Simulation Time of Newer Generation FPGAs SCE-MI Macro-Based Interface for System-on-Chip Verification Verification of Multirate Systems with Multiple Digital Blocks SCE-MI obviously. But which one? Managing Validation and Verification Activities for DO-254 SoC verification made easy with Aldec HES-DVM Q & A with FAA DO-254 DER Randall Fulton Introduction to DO-254 ALINT-PRO-CDC_Finding CDC Issues Aldec DO-254 Solutions Blueprint TySOM Main Design Flow TySOM-1-7Z030 Quick Start Guide Adding Aldec TySOM Board Configurations to Vivado Designing UVM Testbench for Simulation and Emulation of Network-on-Chip Design Xilinx Zynq-based Development Platform for ADAS Synthesis of energy-efficient FSMs implemented in PLD circuits Scaling an IoT network with Aldec Gateway and Amazon AWS Cloud Achieving RTL-to-Netlist Equivalence Partitioning Challenges in Multi-FPGA Prototyping Clock Domain Crossings in the FPGA World Resets and Reset Domain Crossings in ASIC and FPGA designs HDL Simulation Acceleration Solution for Microchip FPGA Designs	Tutorials 01-Creating HDL Text Modules 02-Creating HDL Graphical Modules 03-Design Flow Manager 04-Creating Testbenches 09-Documentation_Features 05-Running Simulation 06-HDL_Debugging 07-Code_Coverage 08-Design_Profiler Running simulation in the Batch mode Running simulation in the GUI mode Library Management TCL Scripting Interface VHDL Performance Optimization Verilog Performance Optimization Waveform Viewer Advanced Dataflow HDE based debugging Debugging Tools X-trace Code Coverage Riviera-PRO Matlab Interface Riviera-PRO Simulink Interface SystemC Simulation Assertions 10-Simulink Interface Course 01 - Getting Started With Active-HDL Course 02 - Running Simulation in the Batch Mode Course 03 - Running Simulation in GUI Mode Course 04 - Library Management Course 05 - VHDL Performance Optimizations Course 06 - Verilog Performance Optimizations Course 07 - Waveform Viewer Course 08 - Advanced Dataflow Course 09 - HDE Based Debugging Course 10 - Debugging Tools Course 11 - XTrace Course 12 - Code Coverage (Statement, Branch, Toggle, Expression Coverage) Course 13 - MATLAB® Interface in Active-HDL Course 14 - Simulink® Interface in Active-HDL Course 15 - Assertions TySOM Design Flow: Creating and Co-debugging a Linux Application using Xilinx SDK and Vivado Logic Analyzer TySOM Design Flow: Verifying custom Vivado IP with Riviera-PRO™ and ALINT-PRO™ Basic UART Interface Tutorial TySOM-1-7Z030 Creating a Hardware and Software Project to Blink LEDs TySOM -1-7Z030 Creating a Hardware and Software Project to Blink LEDs using DIP Switches TySOM -1-7Z030 Enabling GPIO Interrupts Tutorial TySOM-1-7Z030 Programming the TySOM-1-7Z030 Board Using a MicroSD Card TySOM-1-7Z030 Reference Design Part 1: Creating Hardware TySOM-1-7Z030 Reference Design Part 2: Embedded Linux Setup Guide TySOM-2-7Z045 Quick Start Guide TySOM-2-7Z045 Reference Design Part 1: Creating Hardware TySOM-2-7Z045 Reference Design Part 2: Embedded Linux Setup Guide Building and Configuring a Linux OS using the Yocto Project - TySOM-1-7Z030 TySOM IoT Gateway with Amazon Cloud Tutorial - TySOM-1-7Z030 Web Server Tutorial - TySOM-1-7Z030 Wireless Sensor Tutorial - TySOM-1-7Z030 IoT Demo Application Tutorial - TySOM-1-7Z030 01 ALINT-PRO Installation 02 ALINT-PRO Workspace and Projects 03 ALINT-PRO Design Analysis 04 ALINT-PRO Results Analysis 05 ALINT-PRO RTL Schematic 06 ALINT-PRO Command-line and Batch Mode Preparing a Custom Linux Filesystem with Xilinx Petalinux Tools 07 ALINT-PRO Unit Linting with Active-HDL 08 ALINT-PRO Unit Linting with Riviera-PRO How to use Aldec TySOM boards in Xilinx SDx How to use TySOM boards in Xilinx Vivado TySOM Educational Development Kit Connecting Leopard camera to TySOM-3-Zu7EV board using FMC connector How to Run Deep Learning Application on TySOM Board How to use TySOM boards in Xilinx Vivado How to build an FPGA design for Aldec TySOM boards using board definition in Xilinx Vivado How to configure Wi-Fi Direct on TySOM board How to create Wi-Fi access point on TySOM board How to rebuild Aldec demo project in SDx How to use Aldec TySOM boards in Xilinx SDx Running “Hello_World” Application Using AWS IoT Greengrass Core on TySOM Embedded Development Board HES-DVM Proto CE (Cloud Edition) AMI 2.0.0 Thermal Vision Demo HES-DVM Proto CE Product Overview Basic OpenCV Image Processing Tutorial TySOM TySOM XC7Z030 SoC EVB Vivado Embedded Design Development Guide TySOM Embedded Linux Setup Guide Switching BlueEagle Camera Resolution MAC Address Assignment Using U-boot How to rebuild Aldec demo project in SDx How to build an FPGA design for Aldec TySOM boards using board definition in Xilinx Vivado How to add a custom IP core into Aldec TySOM board hardware and update SDx platform Building and Configuring a Linux OS using the Linaro ALINT-PRO Developing Design Constraints for CDC	Technical Specification FMC ADAS CARD Technical Specification FMC-ADAS Technical Specification FMC-INDUSTRIAL Technical Specification FMC-INTF Technical Specification FMC-IoT Technical Specification FMC-NET Technical Specification FMC-QSFP Technical Specification FMC-Vision Technical Specification TySOM-1-7Z030 TySOM-1-7Z030 Overview TySOM-1-7Z030 Technical Specification TySOM-1A-7Z010 Technical Specification TySOM-2-7Z045 TySOM-2-7Z045 + FMC-ADAS + FMC-VISION+ HDR-CMOS TySOM-2-7Z045 + FMC-ADAS + HDR-CMOS Camera Sensor TySOM-2-7Z045 Technical Specification TySOM-2-7Z100 TySOM-2-7Z100 + FMC-ADAS + HDR-CMOS Camera Sensor TySOM-2-7Z100 + FMC-ADAS + FMC-VISION+ HDR-CMOS TySOM-2-7Z100 Technical Specification TySOM-2A-7Z030 + FMC-ADAS + HDR-CMOS Camera Sensor TySOM-2A-7Z030 + FMC-NET TySOM-2A-7Z030 Technical Specification TySOM-3-ZU7 Technical Specification TySOM-3A-ZU19EG Technical Specification TySOM-2A-7Z030 TySOM-M-MPFS250T Technical Specification TySOM-M-MPFS250T Key Features
Case Studies Thales Case Study: Industry’s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance